Add stm32_flash_addr #2
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Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <[email protected]> Signed-off-by: David Ung <[email protected]> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Accept 64 bit addresses from GDB read memory packet. Also allow breakpoint/stepping addresses to take 64bit values. Change-Id: I9bf7b44affe24839cf30897c55ad17fdd29edf14 Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Add new enum ARM_STATE_AARCH64 to the list of possible states. Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8 Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Add new AARCH64 target and ARMv8 support files.
This is an instantiation from the cortex_a files but modified to support
64bit ARMv8. Not all features are complete, notably breakpts and single
stepping are not yet implemented.
Currently it lets you halt of the processors, resume, dump cpu
registers,
read/write memory and getting a stack trace with gdb.
> halt
invalid mode value encountered 5
target state: halted
unrecognized psr mode: 0x5
target halted in ARM state due to debug-request, current mode:
UNRECOGNIZED
cpsr: 0x600001c5 pc: 0x00093528
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* cpu0 aarch64 little cpu.dap halted
> reg
===== arm v8 registers
(0) r0 (/64): 0x00000000FFFFFFED (dirty)
(1) r1 (/64): 0x00000000F76E4000
(2) r2 (/64): 0x0000000000000000
(3) r3 (/64): 0x0000000000010000
(4) r4 (/64): 0xFFFFFFC06E2939E1
(5) r5 (/64): 0x0000000000000018
(6) r6 (/64): 0x003A699CFB3C8480
(7) r7 (/64): 0x0000000053555555
(8) r8 (/64): 0x00FFFFFFFFFFFFFF
(9) r9 (/64): 0x000000001FFEF992
(10) r10 (/64): 0x0000000000000001
(11) r11 (/64): 0x0000000000000000
(12) r12 (/64): 0x00000000000000F0
(13) r13 (/64): 0x00000000EFDFEAC8
(14) r14 (/64): 0x00000000F6DDA659
(15) r15 (/64): 0x0000000000000000
(16) r16 (/64): 0xFFFFFFC0000F9094
(17) r17 (/64): 0x0000000000000000
(18) r18 (/64): 0x0000000000000000
(19) r19 (/64): 0xFFFFFFC00087C000
(20) r20 (/64): 0x0000000000000002
(21) r21 (/64): 0xFFFFFFC000867C28
(22) r22 (/64): 0xFFFFFFC000916A52
(23) r23 (/64): 0xFFFFFFC00116D8B0
(24) r24 (/64): 0xFFFFFFC000774A0C
(25) r25 (/64): 0x000000008007B000
(26) r26 (/64): 0x000000008007D000
(27) r27 (/64): 0xFFFFFFC000080450
(28) r28 (/64): 0x0000004080000000
(29) r29 (/64): 0xFFFFFFC00087FF20
(30) r30 (/64): 0xFFFFFFC000085114
(31) sp (/64): 0xFFFFFFC00087FF20
(32) pc (/64): 0xFFFFFFC000093528
(33) xPSR (/64): 0x00000000600001C5
And from gdb
(gdb) bt
#0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87
erwango#1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107
erwango#2 0x0000000000000000 in ?? ()
Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618
Signed-off-by: David Ung <[email protected]>
Signed-off-by: Matthias Welwarsky <[email protected]>
Enable the use of hardware breakpoint on AARCH64. Change-Id: I59caaa6d92ac60278af8938625b1790a1787372f Signed-off-by: pierre Kuo <[email protected]> Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Ensure that we allow halting debug mode after setting breakpoint Change-Id: I6f0d7a4a4775a93c133fb1ec31dfe3324d9f7395 Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Use AARCH64's hardware step event to do stepping. Change-Id: I2d029ceeadd381913d0c3355c8787b11dacff7f7 Signed-off-by: pierre Kuo <[email protected]> Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
Enable resuming to an address. Change-Id: I29c7d3b56f6cbf8b3cd02c93733fc96f45000af3 Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
When using hardware step for doing stepping, the existing DSCR records the event as external debug request. This will generate a SIGINT event to GDB and causes it to stop the stepping process. For aarch64, read DESR to check if the event is a hardware step and set state to DBG_REASON_SINGLESTEP. With this patch, GDB can now do source level stepping. Change-Id: I1d06f819578c74b3ac17376c67f882adddea1f52 Signed-off-by: David Ung <[email protected]> Signed-off-by: Matthias Welwarsky <[email protected]>
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <[email protected]>
read MPIDR register through correct MSR instruction. Change-Id: I7e2d00c2871191c4168b177a7a809443b0db4c82 Signed-off-by: Matthias Welwarsky <[email protected]>
Some vendors don't fully populate the ROM table, e.g. BCM2357 (used in Raspberry Pi 3) doesn't list CTI, however it is mandatory for halting an ARMv8 core and therefore it's always present (and required), regardless of the ROM table listing it or not. Change-Id: Ia18a4f1b5b931ccd19805b188ebf737c837c6b54 Signed-off-by: Matthias Welwarsky <[email protected]>
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <[email protected]>
Change the signature of aarch64_(read|write)_dcc[_64] to take a "struct armv8_common *" as the context to operate on. No functional change. Change-Id: Ie501113f65ea22aff2eee173ec717f6908a63494 Signed-off-by: Matthias Welwarsky <[email protected]>
- 64bit addresses are supported - Aarch32 state is supported Change-Id: I8c37fa166954d09195d08c6963b8017194e350f5 Signed-off-by: Matthias Welwarsky <[email protected]>
CPUDBG_ -> CPUV8_DBG_ for armv8 debug registers. Change-Id: I3d24cc209309fa9bbeb5c3e6c88a572383c9360e Signed-off-by: Matthias Welwarsky <[email protected]>
Fix 64bit address setting Fix register spacing (16 instead of 4) Set HMC bit for all but linked context match breakpoints, where the bit is ignored anyway Change-Id: I48428f39154a6fe5fadc075ca918d1500a0bb241 Signed-off-by: Matthias Welwarsky <[email protected]>
Use configured CTI base address instead of hardcoded value, if available. Use symbolic constants instead of raw hex offsets. Trim halt and resume code to what is actually necessary. Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed Signed-off-by: Matthias Welwarsky <[email protected]>
Flush DTRRX with a dummy read if it's full, clear sticky errors by writing CSE bit to EDRCR register. Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84 Signed-off-by: Matthias Welwarsky <[email protected]>
The system control register has several instances, depending on the exception level. Make sure to access always access the correct one. Change-Id: I9e867f4dbd9625762042f20ed905064ea4e3270f Signed-off-by: Matthias Welwarsky <[email protected]>
Use opcode definitions from armv8_opcodes.h where appropriate Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8 Signed-off-by: Matthias Welwarsky <[email protected]>
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this bit are ignored but we should not do them anyway - use dpmv8 function to report the reason for debug entry - WFAR is a 64bit register Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de Signed-off-by: Matthias Welwarsky <[email protected]>
Correctly access and parse aarch64 ttbcr. Change-Id: I1b1652791a6b5200f58033925286292d838e8410 Signed-off-by: Matthias Welwarsky <[email protected]>
Use correct instructions to access CLIDR, CSSELR and CCSIDR. Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a Signed-off-by: Matthias Welwarsky <[email protected]>
armv8 breakpoint register spacing is 16, not 4 as in armv7-a Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0 Signed-off-by: Matthias Welwarsky <[email protected]>
Not only null control but also value of the breakpoint when it is removed. Change-Id: Id99c7e3644729c64e563f1fa8b0577f350be6a98 Signed-off-by: Matthias Welwarsky <[email protected]>
Page table layout in aarch64 is very different from armv7-a layout. Remove the incorrect handling, to be replaced correct armv8 code in a later patch Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce Signed-off-by: Matthias Welwarsky <[email protected]>
Aarch64 has 34 registers, but use ARMV8_LAST_REG instead of raw integer constant. Change-Id: I86481899ade74f27fc90eff9f367d444c03e535e Signed-off-by: Matthias Welwarsky <[email protected]>
Aarch64 state has different PSTATE and exception level model. Correct the printout e.g. in poll command. Change-Id: I1820fd1836c7076ae0aa405fa335fd1a14a2e5b3 Signed-off-by: Matthias Welwarsky <[email protected]>
With this patch OpenOCD shuts down properly when errors occur in the server instead of just calling exit(). Change-Id: I2ae1a6153dafc88667951cab9152941cb487be85 Signed-off-by: Marc Schink <[email protected]> Reviewed-on: http://openocd.zylin.com/3223 Reviewed-by: Tomas Vanek <[email protected]> Tested-by: jenkins
Change-Id: I8ce99d7d62dfe3cad63cf6bc68f2faf2234e395c Signed-off-by: Marc Schink <[email protected]> Reviewed-on: http://openocd.zylin.com/3224 Tested-by: jenkins Reviewed-by: Tomas Vanek <[email protected]> Reviewed-by: Freddie Chopin <[email protected]>
Change-Id: I32fed3332857737048dd12da94fcaba140acb726 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4006 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Struct mips32_pracc_context no more in use. In current code cp0 reg/sel do not requires special handling. In sync mode ctx.store_count not used, drop check. In fasdata transfer function use mips32_pracc_read_ctrl_addr() to reduce code. Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4007 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
In most of the cases there is no need to request execution, the check for a new pracc access already does it. Requesting execution if not needed makes execution slower and code larger due the additional checks. Reduce code in fasdata transfer function. Call for execution when exiting debug. Change-Id: I3b45f6d1f62da5fad3e3db84f82a9299b16e1bd9 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4010 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Makes code shorter In fasdata transfer fuction declare variables locally. Avoid cast. Change-Id: I0367b66339560fc20521a0598488e7ff9076808e Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4011 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Implement it as a function, the code was already in. Added optimize option. Change-Id: Ib9ad3f00d6c4f0b91c4e4960a50ec8d102f4e333 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4017 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Less code and probably cleaner. Don't check if it is ever ERROR_OK. Change-Id: I1045b58fd4542ec24430332f49679364ae97b1dc Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4018 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
MacOSX tool chain defines __unused in "sys/cdefs.h", causing a collision. Remove the local define to avoid polluting the compilers internal symbol namespace. Change-Id: I16370c4518e6aeec482dd689e7db80628f846ee3 Signed-off-by: Matthias Welwarsky <[email protected]> Reviewed-on: http://openocd.zylin.com/4118 Reviewed-by: Steven Stallion <[email protected]> Reviewed-by: Freddie Chopin <[email protected]> Reviewed-by: Andreas Fritiofson <[email protected]> Tested-by: jenkins
pracc_list points to an array with code in the lower half and addr in the upper half. Change it to a struct with an instruction field and an address field. Requiered to make reallocation easier. As a side effect the code is less quirky. Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4019 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
If max_code is reached realloc memory. If fails to realloc the error is propagated and every call to pracc_add() returns immediately. The exec function logs the error. Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4020 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
This option is needed, for example, when exiting debug mode in bmips targets. The last instruction is a NOP, not a DERET. When working in async mode this check is not done, mips32_pracc_queue_exec() pass the parameter to mips32_pracc_exec() and never use it. Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4021 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Only reencoded MIPS32 instructions. Added some instructions for crc code. Micromips isa in debug mode is only needed for pic32mm cores. Pic32mz seems that only works with MIPS32 isa when in debug mode. Change-Id: I07059e153a7000ea9204f20b6b37edf6a7623455 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4022 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Needed to run in micromips mode. Seems that if an isa is supported in debug mode it also supported in kernel mode. The contrary is not true. Change-Id: I1feb8e2c376f4db97089f05c20bc0cd177208fb3 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4033 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Read and save configuration registers, up to 4. Config3 holds the micromips implementation info. Added isa implementation info to mips32_common. Added isa filter to avoid common mistakes, but only if one isa mode is implemented. When resuming the isa requested is set if more than one isa mode is implemented. Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4123 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Breakpoint setting based on length (kind) only. Added 16bit aligned 32bit software breakpoints support and same filtering before setting breakpoint. Set the required isa bit in hardware breakpoints. Drop the isa bit in software breakpoints. Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4124 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
There is no need to implement scan code in functions mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32(). Impcode/idcode saved in ejtag.info. Reorder the code in the callers of this functions. Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <[email protected]> Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <[email protected]> Reviewed-by: Freddie Chopin <[email protected]>
Also fixes incorrect comment about MSI range. Change-Id: If1339a00e50db44195dfcd5c767ba3f5d9035451 Signed-off-by: Juha Niskanen <[email protected]> Reviewed-on: http://openocd.zylin.com/4122 Tested-by: jenkins Reviewed-by: Freddie Chopin <[email protected]>
Change-Id: I229c746be27b7c4fa01f48a6ed54ab2679b50ab1 Signed-off-by: Moritz Fischer <[email protected]> Reviewed-on: http://openocd.zylin.com/4109 Tested-by: jenkins Reviewed-by: Paul Fertser <[email protected]>
This patch adds a driver for the SWD-only Cypress KitProg programmer/debugger. Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5 Signed-off-by: Forest Crossman <[email protected]> Reviewed-on: http://openocd.zylin.com/3221 Tested-by: jenkins Reviewed-by: Tomas Vanek <[email protected]>
For some targets (like nrf51) sysfs driver is too slow. This patch implements memory maped driver for IMX processors. Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should work on any NXP IMX CPU. Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7 Signed-off-by: Grzegorz Kostka <[email protected]> Reviewed-on: http://openocd.zylin.com/4106 Tested-by: jenkins Reviewed-by: Paul Fertser <[email protected]>
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <[email protected]> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <[email protected]> Reviewed-by: Paul Fertser <[email protected]>
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <[email protected]> Reviewed-on: http://openocd.zylin.com/4151 Tested-by: jenkins Reviewed-by: Salvador Arroyo <[email protected]>
Signed-off-by: Erwan Gouriou <[email protected]>
This command allows to flash at any sector start address in flash stm32_flsh_addr l4 zephyr.bin 0x8020000 Signed-off-by: Michel Jaouen <[email protected]>
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With this commit the command stm32_flsh_addr is available for flashing at any sector start address
i.e stm32_flsh_addr l4 0x8020000 zephyr.bin