Merge pull request #2161 from VOGL-electronic/expression_slice

gen: fhdl: expression: resolve slice completly

litex/gen/fhdl/expression.py

@@ -96,15 +96,20 @@ def to_signed(r):
 # Print Slice --------------------------------------------------------------------------------------
 
 def _generate_slice(ns, node):
-    assert (node.stop - node.start) >= 1
-    if hasattr(node.value, "__len__") and len(node.value) == 1:
+    length = len(node)
+    assert length >= 1
+    start = 0
+    while isinstance(node, _Slice):
+        start += node.start
+        node = node.value
+    if len(node) == 1:
         sr = "" # Avoid slicing 1-bit Signals.
     else:
-        if (node.stop - node.start) > 1:
-            sr = f"[{node.stop-1}:{node.start}]"
+        if length > 1:
+            sr = f"[{start+length-1}:{start}]"
         else:
-            sr = f"[{node.start}]"
-    r, s = _generate_expression(ns, node.value)
+            sr = f"[{start}]"
+    r, s = _generate_expression(ns, node)
     return r + sr, s
 
 # Print Cat ----------------------------------------------------------------------------------------

litex/gen/fhdl/verilog.py

@@ -456,9 +456,6 @@ def convert(f, ios=set(), name="top", platform=None,
                 msg += f"- {f.name}\n"
             raise Exception(msg)
 
-    # Lower complex slices.
-    f = lower_complex_slices(f)
-
     # Insert resets.
     insert_resets(f)