Merge pull request #2167 from VOGL-electronic/fix_sinals_for_multibit_io

build: common: make sure Signal lenght is right
enjoy-digital · Jan 22, 2025 · ad5d7d3 · ad5d7d3
2 parents 666c9b4 + a019fd4
commit ad5d7d3
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Showing 3 changed files with 5 additions and 5 deletions.
diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
@@ -135,7 +135,7 @@ def lower(dr):
 class AlteraSDRInput:
     @staticmethod
     def lower(dr):
-        return AlteraDDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return AlteraDDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Special Overrides --------------------------------------------------------------------------------
 
@@ -225,7 +225,7 @@ def lower(dr):
 class Agilex5SDRInput:
     @staticmethod
     def lower(dr):
-        return Agilex5DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return Agilex5DDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Agilex5 SDRTristate ------------------------------------------------------------------------------
 

diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
@@ -528,7 +528,7 @@ def lower(dr):
 class LatticeiCE40SDRInput:
     @staticmethod
     def lower(dr):
-        return LatticeiCE40DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return LatticeiCE40DDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # iCE40 SDR Tristate -------------------------------------------------------------------------------
 

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
@@ -255,7 +255,7 @@ def lower(dr):
 class XilinxSDRInputS6:
     @staticmethod
     def lower(dr):
-        return XilinxDDRInputImplS6(dr.i, dr.o, Signal(), dr.clk)
+        return XilinxDDRInputImplS6(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Spartan6 Special Overrides -----------------------------------------------------------------------
 
@@ -323,7 +323,7 @@ def lower(dr):
 class XilinxSDRInputS7:
     @staticmethod
     def lower(dr):
-        return XilinxDDRInputImplS7(dr.i, dr.o, Signal(), dr.clk)
+        return XilinxDDRInputImplS7(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # 7-Series Special Overrides -----------------------------------------------------------------------