Merge branch 'dev' into 'main'

Merge dev branch

* update version string

* Center ILength to make it legible again (5Stage)

* minor svg layering chagnes

* small fixes to single stage svg

* change ctrl color to red

* begin more updates to single stage svg

* Removed some outdated comments

* Changed some path colors and widths

* lower two signals to bottom

* fix wb text bug

* fix svg ids

* update svg directives, ... to include new signals

* update build_svg

* add unedited new single stage svg

* Small svg changes/fixes

* Added directives for the new signals

* Changed the color of control unit signals

* Changed the SVG

* Changed some path widths and colors

* Made 5-stage control signals a bit thicker

* Made 5-stage markers a bit bigger

* Fixed the remaining SVG signals

* Refactored a bit

* Fixed some SVG signals

* Made the svg a bit smaller again

* Moved things around to save horizontal space

* Some more refactoring

* Did some refactoring

* Removed unnecessary text elements from the svg

* Added logic for the WB SVG Directives

* Fix some stuff

* Added the logic for the MEM SVG Directives

* Added logic for the EX SVG Directives

* Added logic for ID svg directives

* Added logic for IF SVG directives

* Added new SvgDirectives; added missing ids to svg

* Add missing id to svg

* Fix dot markers

* Changed to markers for the dots

* Changed signals in the backend which were removed from the SVG

* Added changed markers to svg build script

* Added the new control signals

* Fix read data 1 signal

* Merged some more paths

* Aligned the markers with their boxes

* Fix marker dimensions

* Path start and end can now take same marker

* Changed marker dimensions

* Realigned and merged all (?) path segments that form one path

* updated box stroke widths

* updated the stroke with for all signals

* Merged a path; Made all dots actual circles

* Split up some paths

* use unordered lists

* update text

* reordering and adding notes back

* split instructions into sections

* put tables into component

* format riscv help table

* generate riscv instruction table from json data

* finish accordion riscv help page

* move all sections into accordion

* more collapsibles

* begin implementing accordion for riscv help page

* Added flushes for ecall exit

* Added a test for flushing

* Ecall now continues until the wb stage
But it doesn't flush yet, which is not good

* Added a test for the bug

* update version string

* use unordered lists

* update text

* reordering and adding notes back

* split instructions into sections

* put tables into component

* complete instruction formats

* format riscv help table

* Added flushes for ecall exit

* generate riscv instruction table from json data

* Added a test for flushing

* Ecall now continues until the wb stage
But it doesn't flush yet, which is not good

* Added a test for the bug

* finish accordion riscv help page

* move all sections into accordion

* more collapsibles

* begin implementing accordion for riscv help page

* Center ILength to make it legible again (5Stage)

* minor svg layering chagnes

* small fixes to single stage svg

* update version string

* change ctrl color to red

* begin more updates to single stage svg

* Removed some outdated comments

* Changed some path colors and widths

* lower two signals to bottom

* fix wb text bug

See merge request es/lehre/rechnerarchitektur/architecture-simulator!69

architecture_simulator/gui/riscv_fiveStage_svg_directives.py

@@ -28,10 +28,13 @@ def __init__(self):
         self.InstructionReadAddressText = SvgWriteLeftDirective()
         self.PC = SvgWriteCenterDirective()
         self.FetchPCOut = SvgFillDirectiveBlue()
-        self.FetchAddOutText = SvgWriteCenterDirective()
         self.FetchAddOut = SvgFillDirectiveBlue()
         self.I_LengthText = SvgWriteCenterDirective()
         self.FetchI_Length = SvgFillDirectiveBlue()
+        self.PCFetchOutToExAdder = SvgFillDirectiveBlue()
+        self.PCFetchOutToExMux = SvgFillDirectiveBlue()
+        self.FetchAddOutToPReg = SvgFillDirectiveBlue()
+        self.FetchAddOutToMux = SvgFillDirectiveBlue()
 
 
 class RiscvFiveStageIDSvgDirectives(RiscvSvgDirectivesBase):
@@ -58,10 +61,17 @@ def __init__(self):
         self.DecodeLowerFetchPCOut = SvgFillDirectiveBlue()
         self.DecodeInstructionMemory = SvgFillDirectiveBlue()
         self.ControlUnitLeftRight1_1 = SvgFillDirectiveGreen()
-        self.ControlUnitLeftRight2_1 = SvgFillDirectiveBlue()
+        self.ControlUnitLeftRight2_1 = SvgFillDirectiveGreen()
         self.ControlUnitLeftRight3_1 = SvgFillDirectiveGreen()
         self.ControlUnitLeftRight4_1 = SvgFillDirectiveGreen()
         self.ControlUnitLeft_1 = SvgFillDirectiveGreen()
+        self.DecodeInstructionMemoryIntermediate1 = SvgFillDirectiveBlue()
+        self.DecodeInstructionMemoryIntermediate2 = SvgFillDirectiveBlue()
+        self.ControlUnitRegWriteEnable_1 = SvgFillDirectiveGreen()
+        self.ControlUnitMemWriteEnable_1 = SvgFillDirectiveGreen()
+        self.ControlUnitMemReadEnable_1 = SvgFillDirectiveGreen()
+        self.DecodeInstructionMemoryToAluCtl = SvgFillDirectiveBlue()
+        self.ControlUnitAluOp_1 = SvgFillDirectiveGreen()
 
 
 class RiscvFiveStageEXSvgDirectives(RiscvSvgDirectivesBase):
@@ -90,18 +100,28 @@ def __init__(self):
         self.ExecuteLowerFetchPCOut = SvgFillDirectiveBlue()
         self.ALUComparison = SvgFillDirectiveGreen()
         self.ControlUnitLeftRight1_2 = SvgFillDirectiveGreen()
-        self.ControlUnitLeftRight2_2 = SvgFillDirectiveBlue()
+        self.ControlUnitLeftRight2_2 = SvgFillDirectiveGreen()
         self.ControlUnitLeftRight3_2 = SvgFillDirectiveGreen()
         self.ControlUnitLeftRight4_2 = SvgFillDirectiveGreen()
         self.ControlUnitLeft_2 = SvgFillDirectiveGreen()
-        self.AluControl = SvgFillDirectiveBlue()
+        self.AluControl = SvgFillDirectiveGreen()
+        self.ExecuteImmediateToAdder = SvgFillDirectiveBlue()
+        self.ExecuteImmediateToMux = SvgFillDirectiveBlue()
+        self.ExecuteImmediateInterediate = SvgFillDirectiveBlue()
+        self.ExecuteRegisterFileReadData2ToMux = SvgFillDirectiveBlue()
+        self.ExecuteRegisterFileReadData2ToMemory = SvgFillDirectiveBlue()
+        self.ControlUnitRegWriteEnable_2 = SvgFillDirectiveGreen()
+        self.ControlUnitMemWriteEnable_2 = SvgFillDirectiveGreen()
+        self.ControlUnitMemReadEnable_2 = SvgFillDirectiveGreen()
+        self.ExecuteImmediateToWbMux = SvgFillDirectiveBlue()
+        self.ExecuteInstructionMemoryToAluCtl = SvgFillDirectiveBlue()
+        self.ControlUnitAluOp_2 = SvgFillDirectiveGreen()
 
 
 class RiscvFiveStageMEMSvgDirectives(RiscvSvgDirectivesBase):
     def __init__(self):
         self.Memory = SvgWriteCenterDirective()
         self.DataMemoryAddressText = SvgWriteLeftDirective()
-        self.MemoryExecuteAluResultText = SvgWriteCenterDirective()
         self.MemoryExecuteAluResultText2 = SvgWriteCenterDirective()
         self.MemoryExecuteAluResult = SvgFillDirectiveBlue()
         self.DataMemoryWriteDataText = SvgWriteLeftDirective()
@@ -112,15 +132,21 @@ def __init__(self):
         self.MemoryInstructionMemory4 = SvgFillDirectiveBlue()
         self.MemoryALUComparison = SvgFillDirectiveGreen()
         self.MemoryJumpOut = SvgFillDirectiveGreen()
-        self.MemoryExecuteAddOutText = SvgWriteCenterDirective()
         self.MemoryExecuteAddOut = SvgFillDirectiveBlue()
         self.MemoryFetchAddOutText = SvgWriteCenterDirective()
         self.MemoryFetchAddOut = SvgFillDirectiveBlue()
         self.MemoryImmGenText = SvgWriteCenterDirective()
         self.MemoryImmGen = SvgFillDirectiveBlue()
         self.ControlUnitLeftRight1_3 = SvgFillDirectiveGreen()
-        self.ControlUnitLeftRight2_3 = SvgFillDirectiveBlue()
+        self.ControlUnitLeftRight2_3 = SvgFillDirectiveGreen()
         self.ControlUnitLeft_3 = SvgFillDirectiveGreen()
+        self.MemoryExecuteAluResultToMemory = SvgFillDirectiveBlue()
+        self.MemoryExecuteAluResultToFetchMux = SvgFillDirectiveBlue()
+        self.MemoryExecuteAluResultIntermediate = SvgFillDirectiveBlue()
+        self.MemoryExecuteAluResultToWbMux = SvgFillDirectiveBlue()
+        self.ControlUnitRegWriteEnable_3 = SvgFillDirectiveGreen()
+        self.ControlUnitMemWriteEnable_3 = SvgFillDirectiveGreen()
+        self.ControlUnitMemReadEnable_3 = SvgFillDirectiveGreen()
 
 
 class RiscvFiveStageWBSvgDirectives(RiscvSvgDirectivesBase):
@@ -130,26 +156,20 @@ def __init__(self):
         self.WriteBackMuxOut = SvgFillDirectiveBlue()
         self.RegisterFileWriteRegisterText = SvgWriteLeftDirective()
         self.WriteBackInstructionMemory4 = SvgFillDirectiveBlue()
-        self.WriteBackDataMemoryReadDataText = SvgWriteCenterDirective()
         self.WriteBackDataMemoryReadData = SvgFillDirectiveBlue()
-        self.WriteBackExecuteAluResultText = SvgWriteCenterDirective()
         self.WriteBackExecuteAluResult = SvgFillDirectiveBlue()
-        self.WriteBackFetchAddOutText = SvgWriteCenterDirective()
         self.WriteBackFetchAddOut = SvgFillDirectiveBlue()
-        self.WriteBackImmGenText = SvgWriteCenterDirective()
         self.WriteBackImmGen = SvgFillDirectiveBlue()
         self.wbsrc = SvgWriteCenterDirective()
-        self.ControlUnitLeftRight2_4 = SvgFillDirectiveBlue()
+        self.ControlUnitLeftRight2_4 = SvgFillDirectiveGreen()
+        self.ControlUnitRegWriteEnable_4 = SvgFillDirectiveGreen()
 
 
 class RiscvFiveStageOTHERSvgDirectives(RiscvSvgDirectivesBase):
     def __init__(self):
-        self.FetchRightMuxOutText = SvgWriteCenterDirective()
         self.FetchLeftMuxOutText = SvgWriteCenterDirective()
         self.FetchRightMuxOut = SvgFillDirectiveBlue()
-        self.path2453_0_7_7_9 = SvgFillDirectiveBlue()
-        self.path2453_2_5_7_0_7_5_1_0_4 = SvgFillDirectiveBlue()
-        self.path2453_2_5_7_0_7_6_2_29 = SvgFillDirectiveBlue()
+        self.FetchPCIn = SvgFillDirectiveBlue()
 
 
 class SvgFillDirectiveBlue(SvgFillDirective):
@@ -163,7 +183,7 @@ class SvgFillDirectiveGreen(SvgFillDirective):
     """SVG Fill Directive: highlight: green, default: black"""
 
     def __init__(self):
-        super().__init__(color_on="#008000", color_off="#000000")
+        super().__init__(color_on="#A51E37", color_off="#000000")
 
 
 class SvgWriteLeftDirective(SvgDirective):

architecture_simulator/gui/riscv_single_stage_svg_directives.py

@@ -37,21 +37,26 @@ def __init__(self) -> None:
         # Control Unit paths
 
         # Binary signals
-        self.control_unit_2mux_pc_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen()
-        self.control_unit_to_and_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen()
-        self.alu_control_to_read_data_2mux_path: SvgFillDirectiveGreen = (
-            SvgFillDirectiveGreen()
+        self.control_unit_2mux_pc_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.control_unit_to_and_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.alu_control_to_read_data_2mux_path: SvgFillDirectiveRed = (
+            SvgFillDirectiveRed()
         )
-        self.alu_control_to_read_data_1_mux_path: SvgFillDirectiveGreen = (
-            SvgFillDirectiveGreen()
+        self.alu_control_to_read_data_1_mux_path: SvgFillDirectiveRed = (
+            SvgFillDirectiveRed()
         )
+        self.control_unit_write_data_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.control_unit_read_data_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.control_unit_to_reg_file_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
 
         # Non Binary signals
-        self.control_unit_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
-        self.alu_control_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
-
+        self.control_unit_to_4mux_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.alu_control_to_alu_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
+        self.control_unit_to_alu_control_path: SvgFillDirectiveRed = (
+            SvgFillDirectiveRed()
+        )
         # Other paths
-        self.pc_to_add_instr_len_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
+        self.instr_to_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.pc_to_add_imm_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.pc_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.pc_to_instr_mem_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
@@ -61,36 +66,37 @@ def __init__(self) -> None:
         self.instr_mem_to_read_addr2_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.instr_mem_to_write_reg_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.instr_mem_to_imm_gen_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
+        self.to_immgen_or_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.instr_mem_to_control_unit_path: SvgFillDirectiveBlue = (
             SvgFillDirectiveBlue()
         )
 
         self.imm_gen_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.imm_gen_to_add_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.imm_gen_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
-        self.imm_gen_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
+        self.imm_gen_joint_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
+        self.imm_gen_to_joint_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
 
         self.read_data2_to_mem_write_data_path: SvgFillDirectiveBlue = (
             SvgFillDirectiveBlue()
         )
         self.read_data_1_mux_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.read_data_1_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.read_data_2_2mux_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
-        self.read_data_2_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
+        self.read_data_2_joint_to_2mux_path: SvgFillDirectiveBlue = (
+            SvgFillDirectiveBlue()
+        )
+        self.read_data_2_to_joint_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
 
         self.alu_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.alu_out_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.alu_out_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
-        self.alu_comparison_to_and_path: SvgFillDirectiveGreen = (
-            SvgFillDirectiveGreen()
-        )  # Green since it is a binary value
+        self.alu_comparison_to_and_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
         self.alu_to_data_memory_address_path: SvgFillDirectiveBlue = (
             SvgFillDirectiveBlue()
         )
 
-        self.and_to_mux_path: SvgFillDirectiveGreen = (
-            SvgFillDirectiveGreen()
-        )  # Green since it is a binary value (should be named or!)
+        self.and_to_mux_path: SvgFillDirectiveRed = SvgFillDirectiveRed()
 
         self.add_imm_to_mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
         self.add_instr_len_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue()
@@ -156,8 +162,8 @@ def __init__(self):
         super().__init__(color_on="#0000FF", color_off="#000000")
 
 
-class SvgFillDirectiveGreen(SvgFillDirective):
-    """SVG Fill Directive: highlight: green, default: black"""
+class SvgFillDirectiveRed(SvgFillDirective):
+    """SVG Fill Directive: highlight: red, default: black"""
 
     def __init__(self):
-        super().__init__(color_on="#008000", color_off="#000000")
+        super().__init__(color_on="#A51E37", color_off="#000000")

architecture_simulator/isa/riscv/rv32i_instructions.py

@@ -825,38 +825,56 @@ def behavior(
         self, architectural_state: RiscvArchitecturalState
     ) -> RiscvArchitecturalState:
         """RaiseException(EnvironmentCall)"""
+        result = self.process_ecall(architectural_state)
+        if type(result) is int:
+            architectural_state.exit_code = result
+        elif type(result) is str:
+            architectural_state.output += result
+        return architectural_state
+
+    def process_ecall(self, architectural_state: RiscvArchitecturalState) -> str | int:
+        """Processes this ecall. Returns the action to be applied to the architectural state.
+
+        Args:
+            architectural_state (RiscvArchitecturalState): The state on which the ecall shall be applied.
+
+        Raises:
+            ValueError: Raises an error if the ECALL code is invalid.
+
+        Returns:
+            str|int: Returns either a string to be printed to the output or an exit code.
+        """
         code = int(architectural_state.register_file.registers[17])
         arg = int(architectural_state.register_file.registers[10])
 
         match code:
             case 1:  # print arg as sint
-                architectural_state.output += str(fixedint.Int32(arg))
+                return str(fixedint.Int32(arg))
             case 2:  # print arg as 32-bit float
-                architectural_state.output += str(
-                    unpack(">f", arg.to_bytes(4, "big"))[0]
-                )
+                return str(unpack(">f", arg.to_bytes(4, "big"))[0])
             case 4:  # print null-terminated string stored at address in arg
                 address = arg
+                result = ""
                 while (
                     byte := architectural_state.memory.read_byte(address, False)
                 ) != 0:
-                    architectural_state.output += chr(byte % 128)
+                    result += chr(byte % 128)
                     address += 1
+                return result
             case 11:  # print arg as ascii char
-                architectural_state.output += chr(arg % 128)
+                return chr(arg % 128)
             case 34:  # print arg as hex
-                architectural_state.output += "0x" + "{:X}".format(arg)
+                return "0x" + "{:X}".format(arg)
             case 35:  # print arg as bin
-                architectural_state.output += bin(arg)
+                return bin(arg)
             case 36:  # print arg as uint
-                architectural_state.output += str(arg)
+                return str(arg)
             case 10:  # exit with status 0
-                architectural_state.exit_code = 0
+                return 0
             case 93:  # exit with arg as status
-                architectural_state.exit_code = arg
+                return arg
             case _:
                 raise ValueError(f"{code} (register a7) is not a valid code for ECALL")
-        return architectural_state
 
     def alu_compute(
         self, alu_in_1: int | None, alu_in_2: int | None