Multi-FPGA Integration

[bwintermann]

In this (draft) PR I will slowly add all components required for enabling Multi-FPGA inference. This will mostly be additions and new transformations with the exception of vitis_build.py which needs to be changed almost entirely.

The goal is to keep compatibility to the existing flow so that no changes whatsoever are required to execute FINN as one does usually. Configuration will be done via the existing BuildDataflowConfig. Metadata and node attribute assignments will be named and used as general as possible so that eventual changes or additional ways to utilize multiple FPGAs can be integrated without issue.

[bwintermann]

The following things have to be ported from my private repo to here to enable Multi-FPGA:

• The partitioning transformation that assigns the device id of a given node
• Automatic calculation of the required number of FPGAs
• (Optionally) The SLR assignment transformation that assigns the SLR of a given node based on some constraints
• New CreateStreamingDataflowPartition function that considers SLR and device ID
• The Vitis packaging transformation for the Multi-FPGA communication kernels
• Improving VitisBuild #27 (this includes Multi-FPGA synthesis, parallel synthesis and creation of a large number of different configurations for fast design space exploration)
• Adding graph utility functions #26 would be helpful
• Updating the packaging transformation for the synthesis results
• Integration-readiness: Output metadata required for SLURM interaction and usage of the fast C++ driver https://github.com/eki-project/finn-cpp-driver