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Signed-off-by: Robert Nelson <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,14 +1,31 @@ | ||
| From c069b4083c6e49a60e6d5f639d6f5aba197138ad Mon Sep 17 00:00:00 2001 | ||
| From e9a72d341020db81ee31b7732ae8723e7fbd6f81 Mon Sep 17 00:00:00 2001 | ||
| From: Robert Nelson <[email protected]> | ||
| Date: Wed, 14 Jun 2017 14:01:57 -0500 | ||
| Date: Fri, 16 Jun 2017 10:49:18 -0500 | ||
| Subject: [PATCH] mx6sabresd_spl fixes | ||
|
|
||
| Signed-off-by: Robert Nelson <[email protected]> | ||
| --- | ||
| arch/arm/imx-common/cpu.c | 3 + | ||
| configs/mx6sabresd_spl_defconfig | 6 +- | ||
| drivers/pci/pcie_imx.c | 38 +++++++ | ||
| include/configs/mx6sabre_common.h | 221 ++++++++++++++++++++++++++------------ | ||
| 2 files changed, 155 insertions(+), 72 deletions(-) | ||
| include/pci.h | 4 + | ||
| 5 files changed, 200 insertions(+), 72 deletions(-) | ||
|
|
||
| diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c | ||
| index 40fe813d29..74bdd24ed1 100644 | ||
| --- a/arch/arm/imx-common/cpu.c | ||
| +++ b/arch/arm/imx-common/cpu.c | ||
| @@ -275,6 +275,9 @@ u32 get_ahb_clk(void) | ||
|
|
||
| void arch_preboot_os(void) | ||
| { | ||
| +#if defined(CONFIG_PCIE_IMX) | ||
| + imx_pcie_remove(); | ||
| +#endif | ||
| #if defined(CONFIG_CMD_SATA) | ||
| sata_stop(); | ||
| #if defined(CONFIG_MX6) | ||
| diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig | ||
| index 0e0edefab7..f6e37e9598 100644 | ||
| --- a/configs/mx6sabresd_spl_defconfig | ||
|
|
@@ -37,6 +54,69 @@ index 0e0edefab7..f6e37e9598 100644 | |
| CONFIG_CMD_SF=y | ||
| CONFIG_CMD_I2C=y | ||
| CONFIG_CMD_USB=y | ||
| diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c | ||
| index 732d59d711..eab0a2b602 100644 | ||
| --- a/drivers/pci/pcie_imx.c | ||
| +++ b/drivers/pci/pcie_imx.c | ||
| @@ -42,6 +42,9 @@ | ||
|
|
||
| /* PCIe Port Logic registers (memory-mapped) */ | ||
| #define PL_OFFSET 0x700 | ||
| +#define PCIE_PL_PFLR (PL_OFFSET + 0x08) | ||
| +#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) | ||
| +#define PCIE_PL_PFLR_FORCE_LINK (1 << 15) | ||
| #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) | ||
| #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | ||
| #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) | ||
| @@ -445,6 +448,36 @@ static int imx6_pcie_assert_core_reset(void) | ||
| /* Power up PCIe PHY */ | ||
| setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); | ||
| #else | ||
| + /* | ||
| + * If the bootloader already enabled the link we need some special | ||
| + * handling to get the core back into a state where it is safe to | ||
| + * touch it for configuration. As there is no dedicated reset signal | ||
| + * wired up for MX6QDL, we need to manually force LTSSM into "detect" | ||
| + * state before completely disabling LTSSM, which is a prerequisite | ||
| + * for core configuration. | ||
| + * | ||
| + * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong | ||
| + * indication that the bootloader activated the link. | ||
| + */ | ||
| + if (is_mx6dq()) { | ||
| + u32 val, gpr1, gpr12; | ||
| + | ||
| + gpr1 = readl(&iomuxc_regs->gpr[1]); | ||
| + gpr12 = readl(&iomuxc_regs->gpr[12]); | ||
| + if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) && | ||
| + (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) { | ||
| + val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR); | ||
| + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; | ||
| + val |= PCIE_PL_PFLR_FORCE_LINK; | ||
| + | ||
| + imx_pcie_fix_dabt_handler(true); | ||
| + writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR); | ||
| + imx_pcie_fix_dabt_handler(false); | ||
| + | ||
| + gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2; | ||
| + writel(val, &iomuxc_regs->gpr[12]); | ||
| + } | ||
| + } | ||
| setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); | ||
| clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); | ||
| #endif | ||
| @@ -652,6 +685,11 @@ void imx_pcie_init(void) | ||
| } | ||
| } | ||
|
|
||
| +void imx_pcie_remove(void) | ||
| +{ | ||
| + imx6_pcie_assert_core_reset(); | ||
| +} | ||
| + | ||
| /* Probe function. */ | ||
| void pci_init_board(void) | ||
| { | ||
| diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h | ||
| index 9b0fe5a3c2..c2af5daeb6 100644 | ||
| --- a/include/configs/mx6sabre_common.h | ||
|
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@@ -301,6 +381,21 @@ index 9b0fe5a3c2..c2af5daeb6 100644 | |
|
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| #define CONFIG_ENV_IS_IN_MMC | ||
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| diff --git a/include/pci.h b/include/pci.h | ||
| index d3c955eb80..c8ef997d0d 100644 | ||
| --- a/include/pci.h | ||
| +++ b/include/pci.h | ||
| @@ -754,6 +754,10 @@ int pci_last_busno(void); | ||
| extern void pci_mpc85xx_init (struct pci_controller *hose); | ||
| #endif | ||
|
|
||
| +#ifdef CONFIG_PCIE_IMX | ||
| +extern void imx_pcie_remove(void); | ||
| +#endif | ||
| + | ||
| #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) | ||
| /** | ||
| * pci_write_bar32() - Write the address of a BAR including control bits | ||
| -- | ||
| 2.11.0 | ||
|
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