v0.2.1

doc/conf.py

@@ -37,7 +37,7 @@ def _LatestTagName():
 
 # The full version, including alpha/beta/rc tags
 version = "0.2"     # The short X.Y version.
-release = "0.2.0"   # The full version, including alpha/beta/rc tags.
+release = "0.2.1"   # The full version, including alpha/beta/rc tags.
 try:
 	if _IsUnderGitControl:
 		latestTagName = _LatestTagName()[1:]		# remove prefix "v"

pySystemVerilogModel/__init__.py

@@ -45,15 +45,16 @@
 from pydecor  import export
 
 
-__version__ = "0.2.0"
+__version__ = "0.2.1"
 
 
 @export
 @unique
 class VerilogVersion(Enum):
-	Verilog95 =             95
-	Verilog2001 =         2001
-	Verilog2005 =         2005
+	Any =           -1
+	Verilog95 =     95
+	Verilog2001 = 2001
+	Verilog2005 = 2005
 
 	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
 		95:     Verilog95,
@@ -62,6 +63,7 @@ class VerilogVersion(Enum):
 		1995:   Verilog95,
 		2001:   Verilog2001,
 		2005:   Verilog2005,
+		"Any":  Any,
 		"95":   Verilog95,
 		"01":   Verilog2001,
 		"05":   Verilog2005,
@@ -114,10 +116,11 @@ def __repr__(self):
 @export
 @unique
 class SystemVerilogVersion(Enum):
-	SystemVerilog2005 =         2005
-	SystemVerilog2009 =         2009
-	SystemVerilog2012 =         2012
-	SystemVerilog2017 =         2017
+	Any =                 -1
+	SystemVerilog2005 = 2005
+	SystemVerilog2009 = 2009
+	SystemVerilog2012 = 2012
+	SystemVerilog2017 = 2017
 
 	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
 		5:      SystemVerilog2005,
@@ -128,6 +131,7 @@ class SystemVerilogVersion(Enum):
 		2009:   SystemVerilog2009,
 		2012:   SystemVerilog2012,
 		2017:   SystemVerilog2017,
+		"Any":  Any,
 		"05":   SystemVerilog2005,
 		"09":   SystemVerilog2009,
 		"12":   SystemVerilog2012,

setup.py

@@ -52,7 +52,7 @@
 # Assemble all package information
 setuptools_setup(
 	name=projectName,
-	version="0.2.0",
+	version="0.2.1",
 
 	author="Patrick Lehmann",
 	author_email="[email protected]",