v0.3.4

.github/workflows/Pipeline.yml

@@ -3,6 +3,8 @@ name: Pipeline
 on:
   push:
   workflow_dispatch:
+  schedule:
+    - cron: '0 0 * * 5'
 
 jobs:
 
@@ -109,6 +111,7 @@ jobs:
     needs:
       - Params
       - UnitTesting
+      - PublishTestResults
       - Coverage
       - StaticTypeCheck
       - BuildTheDocs

.gitignore

@@ -8,20 +8,18 @@ __pycache__/
 coverage.xml
 
 # setuptools
-/build/**/*.*
-/dist/**/*.*
+/build/
+/dist/
 /*.egg-info
 
 # Dependencies
 !requirements.txt
 
 # Sphinx
-doc/_build/
-doc/pySystemVerilogModel/**/*.*
-!doc/pySystemVerilogModel/index.rst
+/doc/_build/
+/doc/_theme/
+/doc/pySVModel/**/*.*
+!/doc/pySVModel/index.rst
 
-# BuildTheDocs
-doc/_theme/**/*.*
-
-# IntelliJ project files
+# PyCharm project files
 /.idea/workspace.xml

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+"files.trimTrailingWhitespace": false,
+}

README.md

@@ -25,7 +25,7 @@
 An abstract language model of SystemVerilog (incl. Verilog) written in Python.
 
 
-## Main Goals
+# Main Goals
 
 This package provides a unified abstract language model for SystemVerilog (incl. Verilog).
 Projects reading from source files can derive own classes and implement additional logic to create a concrete language
@@ -35,33 +35,33 @@ Projects consuming pre-processed System Verilog data (parsed, analyzed or elabor
 and services on such a model, while supporting multiple frontends.
 
 
-## Use Cases
+# Use Cases
 
-### pySVModel Generators
+## pySVModel Generators
 
 * See [#11: Interfacing Surelog/UHDM](https://GitHub.com/edaa-org/pySVModel/issues/11)
 
 *TBD*
 
-### pySVModel Consumers
+## pySVModel Consumers
 
 * [Electronic Design Automation Abstraction (EDA²)](https://edaa-org.github.io/)
 
 *TBD*
 
-## Examples
+# Examples
 
-### List all Modules with Parameters and Ports
+## List all Modules with Parameters and Ports
 
 *TBD*
 
-## Contributors
+# Contributors
 
 * [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
 * [Unai Martinez-Corral](https://GitHub.com/umarcor)
 * [and more...](https://GitHub.com/edaa-org/pySVModel/graphs/contributors)
 
-## License
+# License
 
 This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  
 The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).

doc/Makefile

@@ -1,6 +1,3 @@
-CP=cp
-
-# Sphinx options.
 SPHINXOPTS    =
 SPHINXBUILD   = sphinx-build
 PAPER         =
@@ -10,19 +7,5 @@ PAPEROPT_a4     = -D latex_paper_size=a4
 PAPEROPT_letter = -D latex_paper_size=letter
 ALLSPHINXOPTS   = -d $(BUILDDIR)/doctrees -T -D language=en $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
 
-all: html latex
-
-#---
-
-man:
-	$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
-
-#---
-
-html:
-	$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
-
-#---
-
-latex:
-	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
+%:
+	$(SPHINXBUILD) -b $@ $(ALLSPHINXOPTS) $(BUILDDIR)/$@

pySVModel/__init__.py

@@ -45,7 +45,7 @@
 __email__ =     "[email protected]"
 __copyright__ = "2021-2021, Patrick Lehmann"
 __license__ =   "Apache License, Version 2.0"
-__version__ =   "0.3.3"
+__version__ =   "0.3.4"
 
 
 @export

pyproject.toml

@@ -8,3 +8,29 @@ build-backend = "setuptools.build_meta"
 
 [tool.black]
 line-length = 120
+
+[tool.pytest.ini_options]
+# Don't set 'python_classes = *' otherwise, pytest doesn't search for classes
+# derived from unittest.Testcase
+python_files = "*"
+python_functions = "test_*"
+
+[tool.coverage.run]
+branch = true
+omit = [
+	"*site-packages*",
+	"setup.py"
+]
+
+[tool.coverage.report]
+skip_covered = true
+skip_empty = true
+exclude_lines = [
+	"raise NotImplementedError"
+]
+
+[tool.coverage.html]
+directory = "report/coverage/html"
+
+[tool.coverage.xml]
+output = "report/coverage/coverage.xml"

setup.py

@@ -30,7 +30,7 @@
 # ============================================================================
 #
 from pathlib             import Path
-from pyTooling.Packaging import DescribePythonPackageHostedOnGitHub
+from pyTooling.Packaging import DescribePythonPackageHostedOnGitHub, DEFAULT_CLASSIFIERS
 
 gitHubNamespace =        "edaa-org"
 packageName =            "pySVModel"
@@ -44,13 +44,9 @@
 	keywords="Python3 Verilog SystemVerilog Language Model Abstract",
 	sourceFileWithVersion=packageInformationFile,
 	developmentStatus="beta",
-	classifiers=[
-		"Operating System :: OS Independent",
-		"Intended Audience :: Developers",
-		"Topic :: Utilities",
+	classifiers=list(DEFAULT_CLASSIFIERS) + [
 		"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
 		"Topic :: Software Development :: Code Generators",
-		"Topic :: Software Development :: Compilers",
-		"Topic :: Utilities"
+		"Topic :: Software Development :: Compilers"
 	]
 )