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Instruction processors
The opencode processor divides processing of HLASM instruction types into several instruction processors. Each processor is responsible for processing instructions that belong to one instruction type.
As the format of some instruction types can be rather complicated, instruction processors contain Instruction format validation. They check the statement to validate the correctness of the used operand format as well as the correctness of the actual operand values.
During instruction processing, processors work with HLASM expressions. They need to be evaluated to correctly perform the processing.
There are four specialized instruction processors:
| IP | Processed instructions |
|---|---|
| Assembler | *SECT, COM, LOCTR, EQU, DC, DS, COPY, EXTRN, ORG |
| Machine | Instruction format validation only |
| Macro | ANY |
| Conditional Assembly | SET*, GBL*, ANOP, ACTR, AGO, AIF, MACRO, MEND |
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Macro IP
Looks for a macro definition in HLASM context tables and calls it. -
Assembler and Machine IP
Processes assembler and machine instructions to retain consistency in HLASM context tables. -
Conditional Assembly IP
Executes conditional assembly instructions.
I. Project overview
II. Component description
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Language server
4.1 LSP and DAP
4.2 Language server overview
4.3 IO handling
4.4 LSP and DAP server
4.5 Request manager -
Workspace manager
5.1 Parser library API
5.2 Libraries configuration
5.3 Workspace manager overview -
Analyzer
6.1. LSP data collector
6.2. Processing manager
6.2.1 Statement providers
6.2.2 Statement processors
6.2.3 Instruction processors
6.2.4 Expressions
6.3. Instruction format validation
6.4. Lexer
6.5. Parser
6.6. HLASM context tables - Macro tracer
- Extension
III. Dependencies and Build Instructions