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# FPGA_VGA_plane_game | ||
Just a homework. | ||
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这是本学期模拟与数字电路实验课的大作业,使用verilog硬件语言,开发板是Xilinx Nexys4。 | ||
粗略的写了一个飞机大战小游戏,但还是有mygame.v是顶层模块,但是整个程序的reset功能还是有bug,在每次reset的时候显示出来的图片可能被切割。 | ||
由于是第一次用硬件语言写程序,代码风格和架构也很丑,欢迎指正和修改。 | ||
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(.mb文件是提供图片转.ceo文件的一个脚本) |