Skip to content

Commit

Permalink
Reorganize PTP timestamp capture logic; determine PTP clock step size…
Browse files Browse the repository at this point in the history 
… from PTP time instead of parameters

Signed-off-by: Alex Forencich <[email protected]>
  • Loading branch information
@alexforencich
alexforencich committed Feb 13, 2024
1 parent 839fe8c commit baac5f8
Show file tree
Hide file tree
Showing 18 changed files with 181 additions and 226 deletions.
49 changes: 27 additions & 22 deletions rtl/axis_baser_rx_64.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,6 @@ module axis_baser_rx_64 #
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
Expand Down Expand Up @@ -215,6 +213,9 @@ assign crc_valid[2] = crc_next == ~32'he60914ae;
assign crc_valid[1] = crc_next == ~32'he38a6876;
assign crc_valid[0] = crc_next == ~32'h6b87b1ec;

reg [4+16-1:0] last_ts_reg = 0;
reg [4+16-1:0] ts_inc_reg = 0;

assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
Expand Down Expand Up @@ -287,10 +288,6 @@ always @* begin
// idle state - wait for packet
reset_crc = 1'b1;

if (PTP_TS_ENABLE) begin
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end

if (input_type_d1 == INPUT_TYPE_START_0 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
Expand All @@ -312,6 +309,10 @@ always @* begin
reset_crc = 1'b1;
end

if (PTP_TS_ENABLE) begin
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end

if (input_type_d0 == INPUT_TYPE_DATA) begin
state_next = STATE_PAYLOAD;
end else if (input_type_d0[3]) begin
Expand Down Expand Up @@ -410,19 +411,10 @@ always @(posedge clk) begin

if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
lanes_swapped <= 1'b0;
start_packet_reg <= 2'b01;
input_type_d0 <= INPUT_TYPE_START_0;
input_data_d0 <= encoded_rx_data_masked;

if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
lanes_swapped <= 1'b1;
start_packet_reg <= 2'b10;
delay_type_valid <= 1'b1;

if (delay_type_valid) begin
Expand All @@ -431,13 +423,6 @@ always @(posedge clk) begin
input_type_d0 <= INPUT_TYPE_IDLE;
end
input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data};

if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
end else if (lanes_swapped) begin
if (delay_type_valid) begin
input_type_d0 <= delay_type;
Expand Down Expand Up @@ -519,6 +504,23 @@ always @(posedge clk) begin
delay_type <= INPUT_TYPE_ERROR;
end

if (delay_type == INPUT_TYPE_START_0 && delay_type_valid) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
end
end

if (input_type_d0 == INPUT_TYPE_START_0) begin
if (!lanes_swapped) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
end

input_type_d1 <= input_type_d0;
input_data_d1 <= input_data_d0;

Expand All @@ -530,6 +532,9 @@ always @(posedge clk) begin

crc_valid_save <= crc_valid;

last_ts_reg <= ptp_ts;
ts_inc_reg <= ptp_ts - last_ts_reg;

if (rst) begin
state_reg <= STATE_IDLE;

Expand Down
139 changes: 66 additions & 73 deletions rtl/axis_baser_tx_64.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,6 @@ module axis_baser_tx_64 #
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
Expand Down Expand Up @@ -199,6 +197,7 @@ reg [3:0] fcs_output_type_1;

reg [7:0] ifg_offset;

reg frame_start_reg = 1'b0, frame_start_next;
reg frame_reg = 1'b0, frame_next;
reg frame_error_reg = 1'b0, frame_error_next;
reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next;
Expand All @@ -208,12 +207,12 @@ reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;

reg s_axis_tready_reg = 1'b0, s_axis_tready_next;

reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0, m_axis_ptp_ts_adj_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0;
reg m_axis_ptp_ts_valid_reg = 1'b0;
reg m_axis_ptp_ts_valid_int_reg = 1'b0;
reg m_axis_ptp_ts_borrow_reg = 1'b0;

reg [31:0] crc_state_reg[7:0];
wire [31:0] crc_state_next[7:0];
Expand All @@ -224,9 +223,12 @@ reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next;
reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;

reg [1:0] start_packet_reg = 2'b00, start_packet_next;
reg [1:0] start_packet_reg = 2'b00;
reg error_underflow_reg = 1'b0, error_underflow_next;

reg [4+16-1:0] last_ts_reg = 0;
reg [4+16-1:0] ts_inc_reg = 0;

assign s_axis_tready = s_axis_tready_reg;

assign encoded_tx_data = encoded_tx_data_reg;
Expand Down Expand Up @@ -356,6 +358,7 @@ always @* begin

swap_lanes_next = swap_lanes_reg;

frame_start_next = 1'b0;
frame_next = frame_reg;
frame_error_next = frame_error_reg;
frame_min_count_next = frame_min_count_reg;
Expand All @@ -368,31 +371,15 @@ always @* begin
s_tdata_next = s_tdata_reg;
s_empty_next = s_empty_reg;

m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_adj_next = m_axis_ptp_ts_adj_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
m_axis_ptp_ts_valid_int_next = 1'b0;
m_axis_ptp_ts_borrow_next = m_axis_ptp_ts_borrow_reg;

output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;

start_packet_next = 2'b00;
error_underflow_next = 1'b0;

if (s_axis_tvalid && s_axis_tready) begin
frame_next = !s_axis_tlast;
end

if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_next = m_axis_ptp_ts_valid_int_reg;
m_axis_ptp_ts_adj_next[15:0] = m_axis_ptp_ts_reg[15:0];
{m_axis_ptp_ts_borrow_next, m_axis_ptp_ts_adj_next[45:16]} = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_adj_next[47:46] = 0;
m_axis_ptp_ts_adj_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
end

case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
Expand All @@ -408,49 +395,10 @@ always @* begin
s_empty_next = keep2empty(s_axis_tkeep);

if (s_axis_tvalid && cfg_tx_enable) begin
// XGMII start and preamble
if (swap_lanes_reg) begin
// lanes swapped
if (PTP_TS_ENABLE) begin
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
end
start_packet_next = 2'b10;
end else begin
// lanes not swapped
if (PTP_TS_ENABLE) begin
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
end
start_packet_next = 2'b01;
end
if (PTP_TS_ENABLE) begin
if (PTP_TS_CTRL_IN_TUSER) begin
m_axis_ptp_ts_tag_next = s_axis_tuser >> 2;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_next = s_axis_tuser[1];
end else begin
m_axis_ptp_ts_valid_next = s_axis_tuser[1];
end
end else begin
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_next = 1'b1;
end else begin
m_axis_ptp_ts_valid_next = 1'b1;
end
end
end
// Preamble and SFD
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_START_0;
frame_start_next = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
Expand Down Expand Up @@ -641,6 +589,7 @@ always @(posedge clk) begin

swap_lanes_reg <= swap_lanes_next;

frame_start_reg <= frame_start_next;
frame_reg <= frame_next;
frame_error_reg <= frame_error_next;
frame_min_count_reg <= frame_min_count_next;
Expand All @@ -653,14 +602,10 @@ always @(posedge clk) begin

s_axis_tready_reg <= s_axis_tready_next;

m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_adj_reg <= m_axis_ptp_ts_adj_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;

start_packet_reg <= start_packet_next;
start_packet_reg <= 2'b00;
error_underflow_reg <= error_underflow_next;

delay_type_valid <= 1'b0;
Expand Down Expand Up @@ -690,6 +635,50 @@ always @(posedge clk) begin
output_type_reg <= output_type_next;
end

if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_int_reg;
m_axis_ptp_ts_adj_reg[15:0] <= m_axis_ptp_ts_reg[15:0];
{m_axis_ptp_ts_borrow_reg, m_axis_ptp_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_adj_reg[47:46] <= 0;
m_axis_ptp_ts_adj_reg[95:48] <= m_axis_ptp_ts_reg[95:48] + 1;
end

if (frame_start_reg) begin
if (swap_lanes_reg) begin
if (PTP_TS_ENABLE) begin
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
m_axis_ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
m_axis_ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
end
end
start_packet_reg <= 2'b10;
end else begin
if (PTP_TS_ENABLE) begin
m_axis_ptp_ts_reg <= ptp_ts;
end
start_packet_reg <= 2'b01;
end
if (PTP_TS_ENABLE) begin
if (PTP_TS_CTRL_IN_TUSER) begin
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 2;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_reg <= s_axis_tuser[1];
end else begin
m_axis_ptp_ts_valid_reg <= s_axis_tuser[1];
end
end else begin
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 1;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_reg <= 1'b1;
end else begin
m_axis_ptp_ts_valid_reg <= 1'b1;
end
end
end
end

case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
Expand Down Expand Up @@ -765,9 +754,13 @@ always @(posedge clk) begin
crc_state_reg[7] <= 32'hFFFFFFFF;
end

last_ts_reg <= ptp_ts;
ts_inc_reg <= ptp_ts - last_ts_reg;

if (rst) begin
state_reg <= STATE_IDLE;

frame_start_reg <= 1'b0;
frame_reg <= 1'b0;

swap_lanes_reg <= 1'b0;
Expand Down
Loading

0 comments on commit baac5f8

Please sign in to comment.