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Increase the error verbosity of the Verilog parser #965

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Feb 4, 2025
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@kroening kroening commented Feb 4, 2025

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@kroening kroening force-pushed the error-verbose branch 2 times, most recently from 87d9e93 to 8064a9e Compare February 4, 2025 12:17
Bison is instructed to generate verbose error messages for the Verilog parser.

This results in more helpful syntax error messages at least in some cases.
@kroening kroening changed the title Increase the error verbosity of the Verilog and SMV parsers Increase the error verbosity of the Verilog parser Feb 4, 2025
@kroening kroening marked this pull request as ready for review February 4, 2025 12:19
@tautschnig tautschnig merged commit 3579ca1 into main Feb 4, 2025
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@tautschnig tautschnig deleted the error-verbose branch February 4, 2025 19:47
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2 participants