Verilog: rename new_identifier -> any_identifier #950
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kroening
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This renames a production rule in the SystemVerilog grammar to clarify that the identifier matched by the rule does not need to be new.
kroening
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tautschnig
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Jan 29, 2025
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This renames a production rule in the SystemVerilog grammar to clarify that the identifier matched by the rule does not need to be new.