Verilog logical (in)equality expression #593
Conversation
kroening
force-pushed
the
verilog_equality
branch
2 times, most recently
from
d2bd5da to
2c6ff3c
Compare
kroening
force-pushed
the
verilog_equality
branch
from
2c6ff3c to
4120b21
Compare
|
|
||
| tc_binary_expr(expr); | ||
|
|
||
| // This returns 'x' if either of the operands contains x or z. |
There was a problem hiding this comment.
I have to admit that I don't understand how this comment relates to or explains what follows?!
There was a problem hiding this comment.
Maybe by example:
'b0 == 'b0 is 0
'b1x == 'b10 is x
'b1z == 'b1z is x
Hence, if both operands are two-valued, the result is two-valued. If either operand is four-valued, the result is four-valued.
There was a problem hiding this comment.
I understand the example and was assuming as much, but the code that follows just deals with types, it doesn't actually change the expression id or the likes. To me, the comment suggested that the code that follows actually evaluates the expression (or, rather, constructs some code to produce a value for the given operands).
There was a problem hiding this comment.
It does change the ID when it's two-valued -- lines 2431 and 2433.
There was a problem hiding this comment.
Yes, but not in the four-valued case. So I was just a bit confused - but really only by the comment, not the actual implementation.
There was a problem hiding this comment.
Yes, in the four-valued case, the ID stays D_verilog_logical_equality/D_verilog_logical_inequality. I'll add a comment for that.
The Verilog logical equality and inequality now have their own ID as they return a four-valued result when applied to four-valued logic. When applied to two-valued logic, the typechecker maps these to mathematical equality.
kroening
force-pushed
the
verilog_equality
branch
from
4120b21 to
56778dd
Compare
No description provided.