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SystemVerilog: separate scanner and parser state #2032

SystemVerilog: separate scanner and parser state

SystemVerilog: separate scanner and parser state #2032

Triggered via pull request February 4, 2025 11:56
Status Success
Total duration 1m 30s
Artifacts

syntax-checks.yaml

on: pull_request
check-clang-format
1m 19s
check-clang-format
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