Merge pull request #48 from definelicht/link-kernels

Split Compilation and Linking Stages

README.md

@@ -15,9 +15,8 @@ There are a few ways:
 
 #### How do I use it?
 
-Just `#include` the header(s) you are interested in. You can see an example [here](https://github.com/spcl/gemm_hls)!
-
-When a Xilinx hlslib header is included, compilation must allow C++11 features, and the macro `HLSLIB_SYNTHESIS` must be set whenever HLS is run. Set `-cflags "-std=c++11 -DHLSLIB_SYNTHESIS"` in your synthesis script, and `--advanced.prop kernel.<name of your kernel>.kernel_flags="-std=c++11 -DHLSLIB_SYNTHESIS"` when building Xilinx kernels. See the included `xilinx_test/CMakeLists.txt` for reference. 
+Just `#include` the header(s) you are interested in, and/or put the CMake files somewhere in your project directory and
+add their path to your `${CMAKE_MODULE_PATH}`. You can see an example [here](https://github.com/spcl/gemm_hls)!
 
 Officially supported versions of Vitis currently include 2021.1, 2020.2, 2020.1, and 2019.2. Older versions (including SDx and SDAccel) _might_ work, but should be used at your own discretion.
 
@@ -29,7 +28,7 @@ A brief overview of hlslib features is given below.
 
 #### CMake integration
 
-For integrating the Xilinx or Intel HLS tools in your project, the `FindVitis.cmake` and `FindIntelFPGAOpenCL.cmake` are provided in the `cmake` subdirectory. The scripts will set all necessary variables required to build both host and device code. It also provides the `add_vitis_kernel` function, which will produce targets for building hardware emulation, hardware, and synthesis.
+For integrating the Xilinx or Intel HLS tools in your project, the `FindVitis.cmake` and `FindIntelFPGAOpenCL.cmake` are provided in the `cmake` subdirectory. The scripts will set all necessary variables required to build both host and device code. It also provides the `add_vitis_kernel` and `add_vitis_program` functions, which will produce targets for building hardware emulation, hardware, and high-level synthesis.
 
 Example `CMakeLists.txt`:
 ```cmake
@@ -41,7 +40,8 @@ include_directories(${Vitis_INCLUDE_DIRS})
 target_link_libraries(MyHostExecutable ${Vitis_LIBRARIES})
 
 # Will populate the "hw", "hw_emu", and "synthesis" targets
-add_vitis_kernel(MyKernel xilinx_vcu1525_dynamic_5_1 FILES src/MyKernel.cpp)
+add_vitis_kernel(MyKernel FILES src/MyKernel.cpp)
+add_vitis_program(MyKernel xilinx_u250_gen3x16_xdma_3_1_202020_1)
 ```
 
 Kernels can then be built with:
@@ -50,23 +50,34 @@ Kernels can then be built with:
 make hw
 ```
 
-The `add_vitis_kernel` takes a number of optional arguments that can be used to configure the hardware targets:
+The `add_vitis_kernel` and `add_vitis_program` functions takes a number of optional arguments that can be used to configure the hardware targets:
 
 ```cmake
-add_vitis_kernel(MyKernel xilinx_vcu1525_dynamic_5_1
+add_vitis_kernel(MyKernel
                  FILES src/MyKernel.cpp src/MyKernelHelper.cpp
-                 # All flags below this are optional keywords, and any combination of them
-                 # can be specified/not specified
-                 CLOCK 400  # Target a higher clock frequency
-                 KERNEL NameOfKernelFunction  # If different from target name
-                 CONFIG scripts/my_config.cfg  # Given as --config to Vitis
-                 SAVE_TEMPS ON  # Forwards --save-temps to Vitis
+                 # All flags below this are optional keywords, and any
+                 # combination of them can be specified/not specified.
+                 KERNEL MyKernelName  # If different from target name
                  HLS_FLAGS "-DMY_IMPORTANT_DEFINITION -O2"
-                 BUILD_FLAGS "-Os --export_script"
-                 DEBUGGING ON  # Enables Chipscope debugging on all interfaces
-                 PROFILING ON  # Enables profiling for stalls, data transfers, and execution
                  DEPENDS include/MyHeader.h include/OtherDependency.h
-                 INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/include hlslib/include)
+                 INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/include hlslib/include
+                 PORT_MAPPING "ddr0:DDR[0]" "ddr1:DDR[1]")
+add_vitis_kernel(MyOtherKernel
+                 FILES src/MyOtherKernel.cpp)
+add_vitis_program(MyProgram
+                  xilinx_u250_gen3x16_xdma_3_1_202020_1  # Name of Vitis platform
+                  # All flags below this are optional keywords, and any
+                  # combination of them can be specified/not specified.
+                  KERNELS MyKernel       # If KERNELS is not specified, the function checks for a kernel
+                          MyOtherKernel  # with the same name as specified for the program
+                  # Connect multiple linked kernels using streaming interfaces
+                  CONNECTIVITY "MyKernel_1.stream_out:MyOtherKernel_1.stream_in"
+                  CLOCK 400  # Target a different clock frequency than the default
+                  CONFIG scripts/my_config.cfg  # Given as --config to Vitis
+                  SAVE_TEMPS ON  # Forwards --save-temps to Vitis
+                  BUILD_FLAGS "-Os --export_script"
+                  DEBUGGING ON  # Enables Chipscope debugging on all interfaces
+                  PROFILING ON)  # Enables profiling for stalls, data transfers, and execution
 ```
 
 #### DataPack