Initial verilog installation instructions and prelab

fpga/upduino/rules.mk

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+CONS=$(BOARDROOT)/upduino.pcf
+WRAP=$(BOARDROOT)/top.v
+REPORT=report.json
+
+BOARDCLEAN=rm -f *.bin *.json *.asc $(REPORT)
+
+synth: $(TOP).bin
+
+prog: $(TOP).bin
+	sudo iceprog $<
+
+$(TOP).json: $(WRAP) $(SRC)
+	yosys -p 'read_verilog -defer -sv -DTOP=$(TOP) -noautowire $^; hierarchy -top top; synth_ice40 -top top -json $@'
+
+$(TOP).asc $(REPORT) &: $(CONS) $(TOP).json
+	nextpnr-ice40 --report $(REPORT) --up5k --pcf $(CONS) --package sg48 --asc $(TOP).asc --json $(TOP).json
+
+$(TOP).bin: $(TOP).asc
+	icepack $< $@
+
+uart:
+	sudo rmmod ftdi_sio
+	sudo modprobe ftdi_sio
+
+.PHONY: synth prog uart

fpga/upduino/top.v

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+`define CLK_MHZ 48
+
+module top
+    (
+        output wire led_red,
+        output wire led_green,
+        output wire led_blue,
+
+        // output wire gpio_25,
+        // input wire gpio_23,
+        output wire serial_txd,
+        input wire serial_rxd,
+
+        output wire spi_cs
+    );
+
+    assign spi_cs = 1'b1;
+
+    wire clk_sys;
+    SB_HFOSC u_SB_HFOSC (.CLKHFPU(1'b1), .CLKHFEN(1'b1), .CLKHF(clk_sys));
+
+    wire led_r, led_g, led_b;
+
+    `TOP top (
+        .led_r (led_r),
+        .led_g (led_g),
+        .led_b (led_b),
+        .tx (serial_txd),
+        .rx (serial_rxd),
+        .clk (clk_sys),
+        .rst (1'b0)
+    );
+
+    SB_RGBA_DRV rgb (
+        .RGBLEDEN (1'b1),
+        .RGB0PWM  (led_g),
+        .RGB1PWM  (led_b),
+        .RGB2PWM  (led_r),
+        .CURREN   (1'b1),
+        .RGB0     (led_green),
+        .RGB1     (led_blue),
+        .RGB2     (led_red)
+    );
+    defparam rgb.CURRENT_MODE = "0b1";
+    defparam rgb.RGB0_CURRENT = "0b000001";
+    defparam rgb.RGB1_CURRENT = "0b000001";
+    defparam rgb.RGB2_CURRENT = "0b000001";
+endmodule

fpga/upduino/upduino.pcf

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+# The LED pins are on dedicated pins and cannot be modified!
+# Note that they are negative logic (write a 0 to turn on).
+# These are also brought out to the left side of the board. 
+# Cut the board trace on jumper R28 to disable the onboard 3 color LED.
+set_io -nowarn led_green 39
+set_io -nowarn led_red	41
+set_io -nowarn led_blue	40
+
+# FTDI chip interface
+set_io -nowarn serial_txd 14 # FPGA transmit to USB
+set_io -nowarn serial_rxd 15 # FPGA receive from USB
+set_io -nowarn spi_cs 16 # Connected to SPI flash, drive high unless using SPI flash!
+
+# If using the FTDI MPSSE engine, the following signals apply
+set_io -nowarn spi_sck 15  # Shared with the flash
+set_io -nowarn spi_ssn 16  # Connected to SPI flash, drive high unless using SPI flash!
+set_io -nowarn spi_mosi 17 # Shared with the flash
+set_io -nowarn spi_miso 14 # Shared with the flash
+
+# Normal GPIO pins, left side
+set_io -nowarn gpio_23 23
+set_io -nowarn gpio_25 25
+set_io -nowarn gpio_26 26
+set_io -nowarn gpio_27 27
+set_io -nowarn gpio_32 32
+set_io -nowarn gpio_35 35
+set_io -nowarn gpio_31 31
+set_io -nowarn gpio_37 37
+set_io -nowarn gpio_34 34
+set_io -nowarn gpio_43 43
+set_io -nowarn gpio_36 36
+set_io -nowarn gpio_42 42
+set_io -nowarn gpio_38 38
+set_io -nowarn gpio_28 28
+
+# Normal GPIO pins, right side
+
+# Following pins are added on the v3.0 of the board.
+# SPI pins are brought out to the right side of the board
+
+# Note: On board 12MHz clock can be brought to IOB_25B_G3 (pin 20) which is a global
+# clock input. Short across R16 (labelled OSC on the board) to enable 12MHz clock to
+# pin 20.
+set_io -nowarn gpio_20 20
+set_io -nowarn gpio_10 10
+
+# Following are also found on v2.x of the UPduino
+set_io -nowarn gpio_12 12
+set_io -nowarn gpio_21 21
+set_io -nowarn gpio_13 13
+set_io -nowarn gpio_19 19
+set_io -nowarn gpio_18 18
+set_io -nowarn gpio_11 11
+set_io -nowarn gpio_9 9
+set_io -nowarn gpio_6 6
+set_io -nowarn gpio_44 44
+set_io -nowarn gpio_4 4
+set_io -nowarn gpio_3 3
+set_io -nowarn gpio_48 48
+set_io -nowarn gpio_45 45
+set_io -nowarn gpio_47 47
+set_io -nowarn gpio_46 46
+set_io -nowarn gpio_2 2

fpga/verilator.mk

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+sim: $(SIM) $(SRC)
+	verilator -sv -cc --Mdir .verilator $(SRC) --top $(SIM_TOP) --trace --exe --build $< -o ../$(notdir $@)
+
+SIMCLEAN=rm -rf sim .verilator trace.vcd

labs/12-verilog-blink/PRELAB.md

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+# Prelab
+
+In the next two labs you'll learn a bit of SystemVerilog: enough to make some
+basic arithmetic and sequential circuits (lab 1), and a UART
+receiver/transmitter (lab 2).
+
+We'll be using the UPduino FPGA board and open-source tools for simulation and
+synthesis.
+
+In the first lab we'll experiment with making basic circuits. Please look
+through the following resource to get started learning SystemVerilog:
+
+* [docs/sv_guide_240lx.pdf](docs/sv_guide_240lx.pdf)
+
+The first lab will be about applying the concepts from sections 2, 3, and 4.
+The second lab will additionally involve section 5 (finite state machines) to
+build a hardware UART module.
+
+## Toolchain installation
+
+The following open-source tools are needed for UPduino FPGA development:
+
+* Yosys (synthesis engine)
+* NextPNR (place and route tool)
+* Icestorm (bitstream generation for ice40 FPGAs)
+* Verilator (simulator)
+* GTKWave (for displaying waveforms generated by Verilator, optional)
+
+Installing all these tools is a bit of a pain.
+
+**Coming soon**: some prebuilt binaries for the tools.
+
+Scripts for building everything from source are included in the
+`install-scripts` directory. 
+
+<!-- ### Virtual machine (optional) -->
+<!--  -->
+<!-- If you want, you can install these tools in a virtual machine but you will -->
+<!-- probably at least need the IceStorm tools to program the FPGA from outside the -->
+<!-- VM (to avoid needing USB passthrough). You can use a shared folder to share the -->
+<!-- bitstream file between the VM and the host. -->
+<!--  -->
+<!-- A Vagrantfile is provided if you want to experiment with a VM and have -->
+<!-- Vagrant+VirtualBox installed. Unfortunately I haven't been able to get USB -->
+<!-- passthrough to work with this setup. Run `vagrant up` and then `vagrant ssh`. -->
+<!-- The `sync` directory should be shared with the lab directory on the host. -->
+
+## Yosys
+
+Mac:
+
+```
+brew install yosys
+```
+
+Ubuntu:
+
+```
+sudo apt install yosys
+```
+
+Build from source:
+
+```
+git clone https://github.com/YosysHQ/yosys.git yosys
+cd yosys
+make
+sudo make install
+```
+
+## NextPNR (ice40)
+
+```
+git clone https://github.com/YosysHQ/nextpnr nextpnr-ice40
+cd nextpnr-ice40
+cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local .
+make
+sudo make install
+```
+
+## Icestorm
+
+```
+git clone https://github.com/YosysHQ/icestorm.git icestorm
+cd icestorm
+make
+sudo make install
+```
+
+## Verilator
+
+Mac:
+
+```
+brew install verilator
+```
+
+Build from source:
+
+```
+git clone https://github.com/verilator/verilator
+cd verilator
+git checkout stable
+autoconf
+./configure
+make
+sudo make install
+```
+
+## GTKWave (optional)
+
+```
+sudo apt install gtkwave
+```
+
+Website: http://gtkwave.sourceforge.net/

labs/12-verilog-blink/Vagrantfile

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+Vagrant.configure("2") do |config|
+  config.vm.box = "ubuntu/impish64"
+  config.vm.synced_folder ".", "/vagrant"
+  config.vm.synced_folder ".", "/home/vagrant/sync/"
+
+  config.vm.provider "virtualbox" do |vb|
+    vb.memory = "4096"
+    vb.cpus = 2
+    vb.customize ["modifyvm", :id, "--uart1", "0x3F8", "4"]
+    vb.customize ["modifyvm", :id, "--uartmode1", "file", File::NULL]
+  end
+
+  config.vm.provision "shell", inline: <<-SHELL
+    systemctl disable apt-daily.service
+    systemctl disable apt-daily.timer
+  SHELL
+
+  config.vm.provision "shell", inline: "sudo apt-get update", privileged: false
+end

labs/12-verilog-blink/install-scripts/gtkwave.sh

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+sudo apt-get install -y gtkwave

labs/12-verilog-blink/install-scripts/icestorm.sh

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+git clone https://github.com/YosysHQ/icestorm.git icestorm
+cd icestorm
+make
+sudo make install

labs/12-verilog-blink/install-scripts/nextpnr-ice40.sh

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+git clone https://github.com/YosysHQ/nextpnr nextpnr-ice40
+cd nextpnr-ice40
+cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local .
+make
+sudo make install

labs/12-verilog-blink/install-scripts/prereq.sh

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+# icestorm/yosys/nextpnr prereqs
+sudo apt-get install -y build-essential clang bison flex libreadline-dev \
+                     gawk tcl-dev libffi-dev git mercurial graphviz   \
+                     xdot pkg-config python python3 libftdi-dev \
+                     python3-dev libboost-all-dev cmake libeigen3-dev
+
+
+# verilator prereqs
+sudo apt-get install -y git perl python3 make
+sudo apt-get install -y g++  # Alternatively, clang
+sudo apt-get install -y libgz  # Non-Ubuntu (ignore if gives error)
+sudo apt-get install -y libfl2  # Ubuntu only (ignore if gives error)
+sudo apt-get install -y libfl-dev  # Ubuntu only (ignore if gives error)
+sudo apt-get install -y zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
+sudo apt-get install -y ccache  # If present at build, needed for run
+sudo apt-get install -y libgoogle-perftools-dev numactl perl-doc
+sudo apt-get install -y git autoconf flex bison

labs/12-verilog-blink/install-scripts/verilator.sh

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+git clone https://github.com/verilator/verilator
+cd verilator
+git checkout stable
+autoconf
+./configure
+make
+sudo make install

labs/12-verilog-blink/install-scripts/yosys.sh

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+git clone https://github.com/YosysHQ/yosys.git yosys
+cd yosys
+make
+sudo make install