XHFC

Cologne Chip AG's XHFC mISDN driver

The XHFC driver demonstrates the access of the XHFC ISDN controller using the PCI2PI PCI bridge. The XHFC implementation is available within mISDN since November 2005, so you just have to follow the 'Installing mISDN' instructions to retrieve the driver.

source description

layer1 mISDN driver

• xhfc_su.c
• xhfc_su.h

PCI Bridge 'PCI2PI'

• xhfc_pci2pi.c
• xhfc_pci2pi.h

XHFC register definitions

• xhfc24sucd.h

using PCI bridge to access XHFC controller

                    +------ PCI2PI ------+
                    |                    |
+-----------+       |    write_xhfc()    |       +-----------------+
| xhfc_su.c | ----> |     read_xhfc()    | ----> | XHFC controller |
+-----------+       |    sread_xhfc()    |       +-----------------+
                    |  init_pci_bridge() |
                    +--------------------+

The layer1 driver xhfc_su.c calls

• init_pci_bridge() to initialize the bridge
• read_xhfc() to read an XHFC chip register
• write_xhfc() to write an XHFC chip register
• sread_xhfc() to read an XHFC chip ram based register using the so called short read method

Ports, Channels and Fifos

Depending on the XHFC chip model that you are using, there are different numbers of S/T and/or Up line interfaces available. The xhfc_su.c driver detects the XHFC Chip ID and will automatically setup the correct number of ports. Each S/T or Up line interface will be registered as a single mISDN controller. The line interfaces are called port (or pt). The specific port configuration is stored in a xhfc_port_t struct (see xhfc_su.h)

each port (or pt) can use 4 channels : B1, B2, D and PCM

Channel mapping

	B1	B2	D	PCM
pt=0	0	1	2	3
pt=1	4	5	6	7
pt=2	8	9	10	11
pt=3	12	13	14	15

The control variables of a channel can be accessed via xhfc_chan_t, e.g. the D-channel of the second line interface can be accessed with hw->channels[6]. Additionly each channel has a back pointer to the xhfc_port_t that it belongs to, so hw->channels[6].port is 1

Fifo numbers

This channel mapping allows a linear access to the RX and TX FIFO of each channel.

• the TX fifo number is (channel * 2)
• the RX fifo number is (channel * 2) + 1

interrupts, timing

The interrupt sources which are configured in the XHFC sample driver are used the following way:

• timer interrupt:

• check if there is TX data to be sent and fill TX fifos to their max depth

• read out the RX fifos fill state, if it is above threshold, read this data

• fifo interrupt:

• at RX end-of-frame event: read all fifo data although the fill state is below threshold

• S/U interrupt

• handle L1 state changes

The timer interrupt interval has to be fast enough to ensure that there are no RX FIFO overruns while the TX FIFOs cannot underrun when operating at full data rate. In other words: the minimum required interrupt interval depends on the FIFO depth.