Silk

Silk is a new HDL taking inspiration from C++, Java, Verilog, and VHDL.

There are several fundamental requirements for the language:

• The language must be more C "like" than Ada "like"

• The language must not explicitly differentiate between structural, data flow, and behavioral design

• The language must be strongly typed, but allow for implicit conversions

• The language must support templates (Of both types and values)

• The language must allow assignment between ports of "modules" without requiring definition of a wire.

• The language must promote the use of packages but require little effort.

• The language must allow compile time interpretation of files.

• The language must provide a method for compile time asserts

• The language should allow the replacement, or rather the inclusion, of a different standard library that has a different logic structure (such as base 3)

• The language should allow the creation of test benches and execution in an automated manner

• Wouldn't it be great if it was easy to represent Null Convention Logic (Maybe as different std library)

Our language addresses all of these.with the (current) exception of test benches. Test benches are a complex topic that are actively evolving. Significant discussion is required before the language is finalized, emphasis being in simulation.

Detailed Specification