Merge pull request #2676 from clash-lang/bump-verilator

Bump Verilator to v5.020

.ci/docker/Dockerfile

@@ -94,10 +94,10 @@ RUN git clone https://github.com/cliffordwolf/SymbiYosys.git SymbiYosys \
 
 FROM builder AS build-verilator
 
-ARG DEPS_VERILATOR="perl python3 make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev"
+ARG DEPS_VERILATOR="perl python3 make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev help2man"
 RUN apt-get install -y --no-install-recommends $DEPS_VERILATOR
 
-ARG verilator_version="v4.214"
+ARG verilator_version="v5.020"
 RUN git clone https://github.com/verilator/verilator verilator \
   && cd verilator \
   && git checkout $verilator_version \

.ci/docker/build-and-publish-docker-image.sh

@@ -3,9 +3,9 @@
 set -xeo pipefail
 
 REPO="ghcr.io/clash-lang"
-NAME="clash-ci-"
+NAME="clash-ci"
 DIR=$(dirname "$0")
-now=$(date +%F)
+now=$(date +%Y%m%d)
 
 if [[ "$1" == "-y" ]]; then
   push=y
@@ -31,8 +31,7 @@ do
     --build-arg UBUNTU_VERSION=${UBUNTU_VERSION} \
     --build-arg cabal_version=${CABAL_VERSION} \
     --build-arg ghc_version=${GHC_VERSION} \
-    -t "${REPO}/${NAME}${GHC_VERSION}:$now" \
-    -t "${REPO}/${NAME}${GHC_VERSION}:latest" \
+    -t "${REPO}/${NAME}:${GHC_VERSION}-$now" \
     "$DIR"
 done
 
@@ -44,8 +43,7 @@ if [[ $push =~ ^[Yy]$ ]]; then
   for i in "${!GHC_VERSIONS[@]}"
   do
     GHC_VERSION="${GHC_VERSIONS[i]}"
-    docker push "${REPO}/${NAME}${GHC_VERSION}:$now"
-    docker push "${REPO}/${NAME}${GHC_VERSION}:latest"
+    docker push "${REPO}/${NAME}:${GHC_VERSION}-$now"
   done
 else
   echo "Skipping push to container registry"

.ci/gitlab/benchmark.yml

@@ -1,5 +1,5 @@
 .benchmark:
-  image: ghcr.io/clash-lang/clash-ci-$GHC_VERSION:2024-02-15
+  image: ghcr.io/clash-lang/clash-ci:$GHC_VERSION-20240221
   stage: test
   timeout: 2 hours
   variables:

.ci/gitlab/common.yml

@@ -8,13 +8,13 @@ default:
       - stuck_or_timeout_failure
 
 .common:
-  image: ghcr.io/clash-lang/clash-ci-$GHC_VERSION:2024-02-15
+  image: ghcr.io/clash-lang/clash-ci:$GHC_VERSION-20240221
   timeout: 10 minutes
   stage: build
   variables:
     # Note that we copy+paste the image name into CACHE_FALLBACK_KEY. If we don't,
     # $GHC_VERSION gets inserted at verbatim, instead of resolving to some ghc version.
-    CACHE_FALLBACK_KEY: $CI_JOB_NAME-master-ghcr.io/clash-lang/clash-ci-$GHC_VERSION:2024-02-15-2-3-non_protected
+    CACHE_FALLBACK_KEY: $CI_JOB_NAME-master-ghcr.io/clash-lang/clash-ci:$GHC_VERSION-20240221-2-3-non_protected
     GIT_SUBMODULE_STRATEGY: recursive
     TERM: xterm-color
   cache:

.github/workflows/ci.yml

@@ -124,7 +124,7 @@ jobs:
 
     # Run steps inside the clash CI docker image
     container:
-      image: ghcr.io/clash-lang/clash-ci-${{ matrix.ghc }}:2024-02-15
+      image: ghcr.io/clash-lang/clash-ci:${{ matrix.ghc }}-20240221
 
       env:
         THREADS: 2

changelog/2024-02-22T13_45_10+01_00_remove_verilator_shims

@@ -0,0 +1 @@
+REMOVED: Newer Verilators (> v5) can deal with delay statements, hence removing the need for Clash specific workarounds. If you relied on Clash-generated Verilator shims, consider using `verilator --build --binary` instead.

clash-lib/prims/systemverilog/Clash_Explicit_Testbench.primitives.yaml

@@ -17,6 +17,9 @@
       always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin
         if (~ARG[6] !== ~ARG[7]) begin
           $display("@%0tns: %s, expected: %b, actual: %b", $time, ~LIT[5], ~TOBV[~ARG[7]][~TYP[7]], ~TOBV[~ARG[6]][~TYP[6]]);
+          `ifdef VERILATOR
+            $c("std::exit(1);");
+          `endif
           $stop;
         end
       end
@@ -47,10 +50,12 @@
       always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin
         if (~SYM[1] !== ~SYM[2]) begin
           $display("@%0tns: %s, expected: %b, actual: %b", $time, ~LIT[4], ~TOBV[~ARG[6]][~TYP[6]], ~TOBV[~ARG[5]][~TYP[5]]);
+          `ifdef VERILATOR
+            $c("std::exit(1);");
+          `endif
           $stop;
         end
       end
       // pragma translate_on
       assign ~RESULT = ~ARG[7];
       // assertBitVector end
-

clash-lib/prims/systemverilog/Clash_Signal_Internal.primitives.yaml

@@ -100,10 +100,12 @@
       localparam ~GENSYM[half_period][0] = (~PERIOD[0]0 / 2);
       always begin
         ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;
-        `ifndef VERILATOR
         #~LONGESTPERIOD0 forever begin
           ~IF~ISACTIVEENABLE[1]~THEN
           if (~ ~ARG[1]) begin
+            `ifdef VERILATOR
+              $c("std::exit(0);");
+            `endif
             $finish;
           end
           ~ELSE~FI
@@ -112,40 +114,7 @@
           ~RESULT = ~ ~RESULT;
           #~SYM[0];
         end
-        `else
-        ~RESULT = $c("this->~GENSYM[tb_clock_gen][1](",~SYM[0],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");
-        `endif
       end
-
-      `ifdef VERILATOR
-        `systemc_interface
-        CData ~SYM[1](vluint32_t half_period, bool active_rising, bool result_rec) {
-          static vluint32_t init_wait = ~LONGESTPERIOD0;
-          static vluint32_t to_wait = 0;
-          static CData clock = active_rising ? 0 : 1;
-
-          if(init_wait == 0) {
-            if(result_rec) {
-              std::exit(0);
-            }
-            else {
-              if(to_wait == 0) {
-                to_wait = half_period - 1;
-                clock = clock == 0 ? 1 : 0;
-              }
-              else {
-                to_wait = to_wait - 1;
-              }
-            }
-          }
-          else {
-            init_wait = init_wait - 1;
-          }
-
-          return clock;
-        }
-        `verilog
-      `endif
       // pragma translate_on
       // tbClockGen end
     warning: Clash.Signal.Internal.tbClockGen is not synthesizable!
@@ -170,6 +139,9 @@
         #~LONGESTPERIOD0 forever begin
           ~IF~ISACTIVEENABLE[2]~THEN
           if (~ ~ARG[2]) begin
+            `ifdef VERILATOR
+              $c("std::exit(0);");
+            `endif
             $finish;
           end
           ~ELSE~FI
@@ -196,39 +168,10 @@
       // resetGen begin
       // pragma translate_off
       localparam ~GENSYM[reset_period][0] = ~LONGESTPERIOD0 - 10 + (~LIT[2] * ~PERIOD[0]0);
-      `ifndef VERILATOR
       initial begin
         #1 ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 1 ~ELSE 0 ~FI;
         #~SYM[0] ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 0 ~ELSE 1 ~FI;
       end
-      `else
-      always begin
-        // The redundant (~RESULT | ~ ~RESULT) is needed to ensure that this is
-        // calculated in every cycle by verilator. Without it, the reset will stop
-        // being updated and will be stuck as asserted forever.
-        ~RESULT =
-        $c("this->~GENSYM[reset_gen][1](",~SYM[0],",~IF~ISACTIVEHIGH[0]~THENtrue~ELSEfalse~FI)") & (~RESULT | ~ ~RESULT);
-      end
-      `systemc_interface
-      CData ~SYM[1](vluint32_t reset_period, bool active_high) {
-        static vluint32_t to_wait = reset_period;
-        static CData reset = active_high ? 1 : 0;
-        static bool finished = false;
-
-        if(!finished) {
-          if(to_wait == 0) {
-            reset = reset == 0 ? 1 : 0;
-            finished = true;
-          }
-          else {
-            to_wait = to_wait - 1;
-          }
-        }
-
-        return reset;
-      }
-      `verilog
-      `endif
       // pragma translate_on
       // resetGen end
     warning: Clash.Signal.Internal.resetGenN can not be synthesized to hardware!

clash-lib/prims/verilog/Clash_Explicit_Testbench.primitives.yaml

@@ -17,6 +17,9 @@
       always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin
         if (~ARG[6] !== ~ARG[7]) begin
           $display("@%0tns: %s, expected: %b, actual: %b", $time, ~LIT[5], ~ARG[7], ~ARG[6]);
+          `ifdef VERILATOR
+            $c("std::exit(1);");
+          `endif
           $finish;
         end
       end
@@ -47,6 +50,9 @@
       always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin
         if (~SYM[1] !== ~SYM[2]) begin
           $display("@%0tns: %s, expected: %b, actual: %b", $time, ~LIT[4], ~ARG[6], ~ARG[5]);
+          `ifdef VERILATOR
+            $c("std::exit(1);");
+          `endif
           $finish;
         end
       end

clash-lib/prims/verilog/Clash_Signal_Internal.primitives.yaml

@@ -101,10 +101,12 @@
       always begin
         // Delay of 1 mitigates race conditions (https://github.com/steveicarus/iverilog/issues/160)
         #1 ~SYM[0] = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;
-        `ifndef VERILATOR
         #~LONGESTPERIOD0 forever begin
           ~IF~ISACTIVEENABLE[1]~THEN
           if (~ ~ARG[1]) begin
+            `ifdef VERILATOR
+              $c("std::exit(0);");
+            `endif
             $finish(0);
           end
           ~ELSE~FI
@@ -113,41 +115,8 @@
           ~SYM[0] = ~ ~SYM[0];
           #~SYM[1];
         end
-        `else
-        ~SYM[0] = $c("this->~GENSYM[tb_clock_gen][2](",~SYM[1],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");
-        `endif
       end
 
-      `ifdef VERILATOR
-        `systemc_interface
-        CData ~SYM[2](vluint32_t half_period, bool active_rising, bool result_rec) {
-          static vluint32_t init_wait = ~LONGESTPERIOD0;
-          static vluint32_t to_wait = 0;
-          static CData clock = active_rising ? 0 : 1;
-
-          if(init_wait == 0) {
-            if(result_rec) {
-              std::exit(0);
-            }
-            else {
-              if(to_wait == 0) {
-                to_wait = half_period - 1;
-                clock = clock == 0 ? 1 : 0;
-              }
-              else {
-                to_wait = to_wait - 1;
-              }
-            }
-          }
-          else {
-            init_wait = init_wait - 1;
-          }
-
-          return clock;
-        }
-        `verilog
-      `endif
-
       assign ~RESULT = ~SYM[0];
       // pragma translate_on
       // tbClockGen end
@@ -173,6 +142,9 @@
         #~LONGESTPERIOD0 forever begin
           ~IF~ISACTIVEENABLE[2]~THEN
           if (~ ~ARG[2]) begin
+            `ifdef VERILATOR
+              $c("std::exit(0);");
+            `endif
             $finish(0);
           end
           ~ELSE~FI
@@ -201,38 +173,10 @@
       // pragma translate_off
       reg ~TYPO ~GENSYM[rst][0];
       localparam ~GENSYM[reset_period][1] = ~LONGESTPERIOD0 - 10 + (~LIT[2] * ~PERIOD[0]0);
-      `ifndef VERILATOR
       initial begin
         #1 ~SYM[0] = ~IF ~ISACTIVEHIGH[0] ~THEN 1 ~ELSE 0 ~FI;
         #~SYM[1] ~SYM[0] = ~IF ~ISACTIVEHIGH[0] ~THEN 0 ~ELSE 1 ~FI;
       end
-      `else
-      always begin
-        // The redundant (~SYM[0] | ~ ~SYM[0]) is needed to ensure that this is
-        // calculated in every cycle by verilator. Without it, the reset will stop
-        // being updated and will be stuck as asserted forever.
-        ~SYM[0] = $c("this->~GENSYM[reset_gen][2](",~SYM[1],",~IF~ISACTIVEHIGH[0]~THENtrue~ELSEfalse~FI)") & (~SYM[0] | ~ ~SYM[0]);
-      end
-      `systemc_interface
-      CData ~SYM[2](vluint32_t reset_period, bool active_high) {
-        static vluint32_t to_wait = reset_period;
-        static CData reset = active_high ? 1 : 0;
-        static bool finished = false;
-
-        if(!finished) {
-          if(to_wait == 0) {
-            reset = reset == 0 ? 1 : 0;
-            finished = true;
-          }
-          else {
-            to_wait = to_wait - 1;
-          }
-        }
-
-        return reset;
-      }
-      `verilog
-      `endif
       assign ~RESULT = ~SYM[0];
       // pragma translate_on
       // resetGen end