Add scatterUnitWb and gatherUnitWb instances (#220)

clash-lang · Jan 5, 2023 · a0cbc40 · a0cbc40
1 parent 1a5a1dd
commit a0cbc40
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -651,9 +651,13 @@ jobs:
     strategy:
       matrix:
         target:
+          - {top: callisto3,                   stage: netlist}
+          - {top: gatherUnit1K,                stage: hdl}
+          - {top: gatherUnit1KReducedPins,     stage: netlist}
+          - {top: scatterUnit1K,               stage: hdl}
+          - {top: scatterUnit1KReducedPins,    stage: netlist}
           - {top: switchCalendar1k,            stage: hdl}
           - {top: switchCalendar1kReducedPins, stage: netlist}
-          - {top: callisto3,                   stage: netlist}
 
     container:
       image: ghcr.io/clash-lang/clash-ci-9.0.2:2022-02-02

diff --git a/bittide-instances/bin/Shake.hs b/bittide-instances/bin/Shake.hs
@@ -25,6 +25,7 @@ import qualified Bittide.Instances.Calendar as Calendar
 import qualified Bittide.Instances.ClockControl as ClockControl
 import qualified Bittide.Instances.ElasticBuffer as ElasticBuffer
 import qualified Bittide.Instances.MVPs as MVPs
+import qualified Bittide.Instances.ScatterGather as ScatterGather
 import qualified Bittide.Instances.Si539xSpi as Si539xSpi
 import qualified Bittide.Instances.StabilityChecker as StabilityChecker
 import qualified Bittide.Instances.Synchronizer as Synchronizer
@@ -73,6 +74,10 @@ targets =
   , 'ClockControl.callisto3
   , 'ElasticBuffer.elasticBuffer5
   , 'MVPs.clockControlDemo0
+  , 'ScatterGather.gatherUnit1K
+  , 'ScatterGather.gatherUnit1KReducedPins
+  , 'ScatterGather.scatterUnit1K
+  , 'ScatterGather.scatterUnit1KReducedPins
   , 'Si539xSpi.si5391Spi
   , 'StabilityChecker.stabilityChecker_3_1M
   , 'Synchronizer.safeDffSynchronizer

diff --git a/bittide-instances/bittide-instances.cabal b/bittide-instances/bittide-instances.cabal
@@ -97,6 +97,7 @@ library
     Bittide.Instances.ElasticBuffer
     Bittide.Instances.Hacks
     Bittide.Instances.MVPs
+    Bittide.Instances.ScatterGather
     Bittide.Instances.Si539xSpi
     Bittide.Instances.StabilityChecker
     Bittide.Instances.Synchronizer

diff --git a/bittide-instances/src/Bittide/Instances/ScatterGather.hs b/bittide-instances/src/Bittide/Instances/ScatterGather.hs
@@ -0,0 +1,104 @@
+-- SPDX-FileCopyrightText: 2022 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+{-# OPTIONS_GHC -fconstraint-solver-iterations=7 #-}
+
+module Bittide.Instances.ScatterGather where
+
+import Clash.Prelude
+
+import Bittide.Calendar
+import Bittide.Instances.Domains
+import Bittide.Instances.Hacks
+import Bittide.ScatterGather
+import Bittide.SharedTypes
+import Protocols.Wishbone
+
+type FrameWidth = 64
+type NLinks = 16
+type WishboneAddrWidth = 32
+type WishboneWidth = 4
+
+scatterCal1K :: ScatterConfig WishboneWidth WishboneAddrWidth
+scatterCal1K = ScatterConfig cal
+ where
+  cal :: CalendarConfig WishboneWidth WishboneAddrWidth (Index 1024)
+  cal = CalendarConfig (SNat @1024)
+    (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil)
+    (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil)
+
+gatherCal1K :: GatherConfig WishboneWidth WishboneAddrWidth
+gatherCal1K = GatherConfig cal
+ where
+  cal :: CalendarConfig WishboneWidth WishboneAddrWidth (Index 1024)
+  cal = CalendarConfig (SNat @1024)
+    (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil)
+    (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil)
+
+{-# ANN scatterUnit1K
+  (Synthesize
+    { t_name = "scatterUnit1K"
+    , t_inputs =
+      [ PortName "clk"
+      , PortName "rst"
+      , PortName "wbInCal"
+      , PortName "linkIn"
+      , PortName "wbInSu"
+      ]
+    , t_output = PortProduct ""
+      [ PortName "wbOutSu"
+      , PortName "wbOutCal"
+      ]
+    }
+  )#-}
+scatterUnit1K ::
+  Clock Basic200 ->
+  Reset Basic200 ->
+  Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) ->
+  Signal Basic200 (DataLink 64) ->
+  Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) ->
+  ( Signal Basic200 (WishboneS2M (Bytes WishboneWidth))
+  , Signal Basic200 (WishboneS2M (Bytes WishboneWidth)))
+scatterUnit1K clk rst = withClockResetEnable clk rst enableGen $ scatterUnitWb scatterCal1K
+{-# NOINLINE scatterUnit1K #-}
+
+scatterUnit1KReducedPins ::
+  Clock Basic200 -> Reset Basic200 -> Signal Basic200 Bit -> Signal Basic200 Bit
+scatterUnit1KReducedPins clk rst =
+  withClockResetEnable clk rst enableGen $ reducePins scatterUnit1K'
+ where
+  scatterUnit1K' (unbundle -> (a,b,c)) = bundle $ scatterUnit1K clk rst a b c
+
+{-# ANN gatherUnit1K
+  (Synthesize
+    { t_name = "gatherUnit1K"
+    , t_inputs =
+        [ PortName "clk"
+        , PortName "rst"
+        , PortName "wbInCal"
+        , PortName "wbInGu"
+        ]
+    , t_output = PortProduct ""
+        [ PortName "linkOut"
+        , PortName "wbOutGu"
+        , PortName "wbOutCal"
+        ]
+    }
+  )#-}
+gatherUnit1K ::
+  Clock Basic200 ->
+  Reset Basic200 ->
+  Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) ->
+  Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) ->
+  ( Signal Basic200 (DataLink 64)
+  , Signal Basic200 (WishboneS2M (Bytes WishboneWidth))
+  , Signal Basic200 (WishboneS2M (Bytes WishboneWidth)))
+gatherUnit1K clk rst = withClockResetEnable clk rst enableGen $ gatherUnitWb gatherCal1K
+{-# NOINLINE gatherUnit1K #-}
+
+gatherUnit1KReducedPins ::
+  Clock Basic200 -> Reset Basic200 -> Signal Basic200 Bit -> Signal Basic200 Bit
+gatherUnit1KReducedPins clk rst =
+  withClockResetEnable clk rst enableGen $ reducePins gatherUnit1K'
+ where
+  gatherUnit1K' (unbundle -> (a,b)) = bundle $ gatherUnit1K clk rst a b