Why is certain clock frequency producing protocol violations?

[nileshbpat]

Observation is,
There is a functional dependence on core clock frequency.
In general, design is not working at lower frequencies (i.e. 100MHz).
For 500Mhz, we're seeing the following error, which points to dependency on the programmed frequency.
Error > Clock in to Data Out for Slave(16.990ns) is more than tSCO(12.000ns)