Add Vexriscv/Litex designs for Oxide: No CFU / Trivial CFU / hps_accel CFU

[tcal-x]

The LiteX-generated Verilog is target-specific, and can be copied from the gateware/ directory after a build in CFU Playground.

For no CFU:

cd proj/proj_template_v
make PLATFORM=hps EXTRA_LITEX_ARGS="--cpu-variant=full"   clean bitstream

For trivial CFU:

cd proj/proj_template_v
make PLATFORM=hps EXTRA_LITEX_ARGS="--cpu-variant=slim+cfu"   clean bitstream

For big CFU:

cd proj/hps_accel
make PLATFORM=hps EXTRA_LITEX_ARGS="--cpu-variant=slim+cfu"   clean bitstream

The generated Verilog and constraints files will be found in soc/build/hps.{proj_template_v,hps_accel}/gateware/.

Look in the Yosys command file (*.ys) for the reference to the correct VexRiscv Verilog for the design.

@kgugala , can you assign this to someone.