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syntax error(s) when parsing low Firrtl #2537

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wky17 opened this issue Aug 6, 2022 · 0 comments
Open

syntax error(s) when parsing low Firrtl #2537

wky17 opened this issue Aug 6, 2022 · 0 comments

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@wky17
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wky17 commented Aug 6, 2022

when I try to parser the following low Firrtl code through treadle, 2 syntax error(s) detected.

the low Firrtl code:

circuit Accumulator : @[:@2.0]
module Accumulator : @[:@3.2]
input clock : Clock @[:@4.4]
input reset1 : UInt < 1 > @[:@5.4]
input io_in : UInt < 1 > @[:@6.4]
output io_out : UInt < 8 > @[:@6.4]

reg accumulator : UInt < 8 > , clock with :
  reset => ( UInt < 1 > ( "h0" ) , accumulator ) @[Accumulator.scala 16:28:@8.4]
node _T_11 = add ( accumulator , io_in ) @[Accumulator.scala 17:30:@9.4]
node _T_12 = tail ( _T_11 , 1 ) @[Accumulator.scala 17:30:@10.4]
io_out <= accumulator @[Accumulator.scala 18:10:@12.4]
accumulator <= mux ( reset1 , UInt < 8 > ( "h0" ) , _T_12 ) @[Accumulator.scala 17:15:@11.4]

when I try to parse it with treadle using: TreadleTestHarness(Seq(FirrtlSourceAnnotation(accuFirrtl)))
the error is:

line 11:21 mismatched input '(' expecting {'circuit', 'module', 'extmodule', 'input', 'output', 'UInt', 'SInt', 'Fixed', 'Interval', '.', 'Clock', 'AsyncReset', 'Reset', 'Analog', '[', 'flip', 'parameter', 'reset', 'wire', 'reg', 'with', 'mem', 'cmem', 'smem', 'mport', 'inst', 'of', 'node', 'is', 'invalid', 'stop(', 'printf(', 'skip', 'attach', 'assert', 'assume', 'cover', 'depth', 'reader', 'writer', 'readwriter', 'when', 'else', 'infer', 'read', 'write', 'rdwr', 'old', 'new', 'undefined', 'stop', 'printf', 'mux', 'validif', FileInfo, Id, NEWLINE, DEDENT}
line 15:4 extraneous input '' expecting
Exception in thread "main" firrtl.SyntaxErrorsException: 2 syntax error(s) detected
1 targets failed
playground.run subprocess failed
截屏2022-08-06 20 59 39

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