Release 1.1 sign-off checklist

[calebofearth]

Overview

This issue tracks the outstanding items to complete prior to finalizing the 1.1 release version, and provides public visibility to the sign-off protocol used for releases.
Discussions among contributors have been ongoing to agree on the proposed changes in any outstanding Pull Requests, in order to converge all required tests and sign-off protocols.

Checklist

• Regressions sign-off from Microsoft (after finalizing all PRs) @calebofearth
• Coverage sign-off @calebofearth
• FPGA validation (Luke Mahowald)
• Update HW Rev ID, HW_CONFIG registers @calebofearth
• Complete Lint review @nstewart-amd
• Complete CDC review @nstewart-amd
• Complete RDC review @amullick007
• Formal Verification review @mojtaba-bisheh
• Update documentation
  • Add revised lint rules to integration specification @nstewart-amd @Nitsirks
  • Add CDC constraints to integration specification @nstewart-amd
  • Add RDC constraints/waivers to integration specification @amullick007
  • Update release notes @calebofearth
  • README updates @calebofearth
    • Add CDC tool version @nstewart-amd
    • Add RDC tool version @amullick007
  • Add latest synthesis results to the integration specification @nstewart-amd
• Firmware update regarding FIPS compliance and hw requirements @JohnTraverAmd
  • NOTE: FIPS compliance pending approval of HMAC384 algorithm instead of HMAC512 - discussion with FIPS WG
• Tag the main branch with 1.1 @calebofearth
• Create 1.1 branch for FW regression consumption

Pending Pull Requests to complete

• Issue 445 LINT fixes #461 (CLOSE do not merge!)
• Adding default branch in unique case statements to resolve FMR_ELAB-131 warnings in Formality #501 (CLOSE do not merge! Proposed change will not be accepted)
• Additional round of lint cleanup #483
• [RDL] Add LMS enable bit, update hw_rev_id to 1.1, regenerate RDL #486
• [UVM] Update UVM ROM test with bringup fixes, infra to test latest public builds, auto-extract PK values #478
• [SVA] Fix check on zeroize operation #489
• Resolving unnamed generate blocks Lint warnings #510
• Fix for truncated bits after casting logical shifts to the incorrect width for lint fixes #524
• KeyVault fixes and JTAG fix #528
• Fix for issue #523 - JTAG under reset during breakpoint #541
• Remove library-defined clog2 function #533
• Update HWReleaseProcess to allow RTL tagging independent of SW Caliptra#196
• Add clock security requirements #519
• Update CDC Constraint in CaliptraIntegrationSpecification.md #534
• Update CDC version in README.md #535
• Update Synthesis Results CaliptraIntegrationSpecification.md #536
• Update CaliptraIntegrationSpecification.md #539
• Fix up JTAG reset in integration specification #546
• [Docs] Updated release notes and doc version for 1.1 #496

[calebofearth]

@amullick007 : please link to the generate-label PR if you plan to submit it
EDIT: added #510 to checklist

[calebofearth]

@nsteward-amd: Please update here on the status/urgency of #446
UPDATE: Resolved

[calebofearth]

Crypto formal verification: Completed by Lubis EDA.

[amullick007]

Added PR #511 for RDC documentation updates

[nstewart-amd]

1.1 LINT Signoff run results:
Flow | Violation Count | Breakdown | Comments
LINT | 1622 |
1617 – ImproperRangeIndex-ML | Known false violations CASE ID: 01648779
3 – NTL_RST05 | Known reset synchronizer violation.
2 – STARC05-1.3.2.2 | Known reset synchronizer violation.

1.1 LINT analysis is considered complete.

[nstewart-amd]

1.1 CDC Signoff run results:
Flow | Violation Count | Breakdown | Comments
CDC | 0 | Clean | Clean

1.1 CDC analysis is complete and pass.

[nstewart-amd]

I've added PR's for #534 #535 #536

[jlmahowa-amd]

FPGA tests are passing.

• SW repo test for hw_rev needs to be updated for 1.1
• Manually checked that BOOT_WAIT flow over JTAG works on FPGA. This is done without CG enabled so might not cover Failed to deassert the reset of uc using JTAG for HVM #523.

[nstewart-amd]

<style> </style>

Flow	Violation Count	Breakdown	Comments
LINT	1612	1612 – ImproperRangeIndex-ML	Known false violations CASE ID: 01648779
LINT	6	6 – UnrecSynthDir-ML	Files: •caliptra_prim_lc_sync.sv •caliptra_prim_mubi4_sync.sv •caliptra_prim_mubi8_sync.sv Code: •// pragma coverage on •// pragma coverage off •RECOMMEND WAIVE
CDC	0	Clean	Clean

<style> </style>

Synthesis	Timing	Formality	Stdcell Area	Memory Area	Total Area	Comment
1.0	PASSED	PASSED	86665	239937	334473
1.1	-17.18ps (496MHz Achieved)	PASSED	93418	239937	341226	Critical path ICCM SRAM->DCCM SRAM

[calebofearth]

Release 1.1 has been tagged.
This issue will remain open pending the final checklist item, chipsalliance/Caliptra#196.