Caliptra Synthesis Errors

[amullick007]

We are getting below synthesis errors with latest RTL.

Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[6]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[5]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[4]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[3]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[2]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[1]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'el2_ifu_mem_ctl__449949_NV_caliptra', input pin 'din[0]' of hierarchical cell 'perr_dat_ff' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)

Upon checking the RTL, I saw that perf_dat_ff.din[6:0] is connected to ifu_ic_rw_int_addr_ff[12:6]. The driver of ifu_ic_rw_int_addr_ff is coming from below module code which is disabled because pt.ICACHE_ENABLE is 0.

         rvdffie #(pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO+pt.ICACHE_NUM_WAYS+1) tag_addr_ff (.*,
                                                                                              .clk(free_l2clk),
                                                                                              .din({ifu_ic_rw_int_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO],
                                                                                                    ifu_tag_wren_w_debug[pt.ICACHE_NUM_WAYS-1:0],
                                                                                                    ic_valid_w_debug}),
                                                                                              .dout({ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO],
                                                                                                     ifu_tag_wren_ff[pt.ICACHE_NUM_WAYS-1:0],
                                                                                                     ic_valid_ff})
                                                                                              );

Is it ok for synthesis to treat the input din of perr_dat_ff as 0?

[Nitsirks]

Yes, it has no loads that I can find with icache disabled.

We're adding moving this flop to a list of requests for VeeR team to implement.

[amullick007]

@Nitsirks Is this issue resolved in RTL1.0 release?

[Nitsirks]

No. Looks like there is a PR out for VeeR that will fix it. I assume we'll absorb this for 1.1

chipsalliance/Cores-VeeR-EL2#149

[amullick007]

Thanks Michael, do you know the approximate timeline for 1.1 release?

[bharatpillilli]

@Nitsirks - close this?

[calebofearth]

Fixed for 1.1 release in 020cdc6 via #483