Neuromorphic Network-on-Chip Architecture for Spiking Neural Networks

Description

This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.

Team Members

1. E/17/018 Balasuriya I.S. [Website, Email]
2. E/17/154 Karunanayake A.I. [Website, Email]
3. E/17/286 Rathnayaka R.M.T.N.K. [Website, Email]

Supervisors

1. Dr. Isuru Nawinne [Website, Email]
2. Dr. Mahanama Wickramasinghe [Website, Email]
3. Prof. Roshan Ragel [Website, Email]
4. Dr. Isuru Dasanayake [Website, Email]

Links

1. Project Page
2. Github Repo
3. Department of Computer Engineering