Update descriptions

README.md

@@ -6,8 +6,8 @@
 
 <p align="center">
 <picture>
-  <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/simon1hofmann/mnt-bench/main/img/mnt_light.svg" width="60%">
-  <img src="https://raw.githubusercontent.com/simon1hofmann/mnt-bench/main/img/mnt_dark.svg" width="60%">
+  <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/cda-tum/mnt-bench/main/img/mnt_light.svg" width="60%">
+  <img src="https://raw.githubusercontent.com/cda-tum/mnt-bench/main/img/mnt_dark.svg" width="60%">
 </picture>
 </p>
 
@@ -34,8 +34,8 @@ See the [benchmark description](https://www.cda.cit.tum.de/mntbench/benchmark_de
 
 So far, MNT Bench supports the following native gate-sets:
 
-1. [QCA ONE]() gate set: _\[AND, OR, NOT\]_
-2. [Bestagon]() gate set: _\[AND, OR, NOT\]_
+1. [QCA ONE]() gate set: _\[AND, OR, NOT, BUF\]_
+2. [Bestagon]() gate set: _\[AND, NAND, OR, NOR, XOR, XNOR, NOT, BUF\]_
 
 ## Clocking Schemes
 

pyproject.toml

@@ -63,9 +63,9 @@ dev = ["mnt.bench[coverage, docs]"]
 "mnt.bench" = "mnt.benchviewer.main:start_server"
 
 [project.urls]
-Homepage = "https://github.com/simon1hofmann/mntbench"
-"Bug Tracker" = "https://github.com/simon1hofmann/mntbench/issues"
-Discussions = "https://github.com/simon1hofmann/mntbench/discussions"
+Homepage = "https://github.com/cda-tum/mntbench"
+"Bug Tracker" = "https://github.com/cda-tum/mntbench/issues"
+Discussions = "https://github.com/cda-tum/mntbench/discussions"
 Research = "https://www.cda.cit.tum.de/research/fcn/"
 
 [tool.setuptools_scm]

src/mnt/benchviewer/templates/description.html

@@ -73,17 +73,25 @@ <h1>MNT Bench: Library Description and File Format</h1>
         <li><em>QCA ONE</em>: Used for QCA circuits.</li>
         <li><em>Bestagon</em>: Used for SiDB circuits.</li>
       </ul>
+      <p>and up to five different clocking schemes:</p>
+      <ul>
+        <li><em>2DDWave</em></li>
+        <li><em>USE</em></li>
+        <li><em>RES</em></li>
+        <li><em>ESR</em></li>
+        <li><em>ROW</em></li>
+      </ul>
       <p>Used File Format:</p>
       <ul>
         <li>
           Not every benchmark is necessarily available for every possible
           configuration of the available options. For example, for large
-          circuits layouts using the USE clocking scheme have not been found
+          circuits, layouts using the USE clocking scheme have not been found
           yet.
         </li>
         <li>
           Since the <em>.zip</em> file may be composed of numerous files
-          (currently, we offer more than 100 benchmark circuits), the following
+          (currently, we offer more than 150 benchmark circuits), the following
           naming convention is used for the respective files:
         </li>
       </ul>

src/mnt/benchviewer/templates/index.html

@@ -80,7 +80,23 @@
     </p>
     <div class="container">
       <h1>Welcome to the Munich Nanotech Benchmark Library (MNT Bench)!</h1>
-      <p>ToDo: Description.</p>
+      <p>
+        The development and improvement of physical design tools for
+        Field-coupled Nanocomputing (FCN) are crucial for the success of this
+        emerging technology. To compare the results of new physical design
+        algorithms, this benchmark suite offers common benchmark functions in
+        the domain combined with the state-of-the-art layouts. On top of layouts
+        using different gate sets, such as the gate library QCAOne for
+        Quantum-dot Cellular Automata (QCA) or Bestagon for Silicon Dangling
+        Bonds (SiDBS), the following benchmark library also differentiates
+        between different underlying clocking schemes like 2DDWave, USE, RES,
+        ESR or ROW.
+      </p>
+      <p>
+        All layouts can be downloaded as fiction gate -level layouts files
+        (.fgl), which can be read and written with
+        <a href="https://github.com/cda-tum/fiction">fiction</a>.
+      </p>
 
       <p>
         In order to create a benchmark set according to your needs, simply fill
@@ -198,9 +214,12 @@ <h6 style="margin-bottom: 0px">EPFL Benchmarks:</h6>
         </div>
 
         <div class="col-md-12" style="height: 20px"></div>
-        <h4>Abstraction Level Selection</h4>
+        <h4>Technology Selection</h4>
         <p class="text-justify" style="margin: 0px">
-          ToDo. For details, see
+          Next, technological specifications for the selected benchmarks must be
+          chosen. The gate library defines the selection of gates that can be
+          used, while the clocking scheme defines the underlying arrangement of
+          clock zones on the layout. For details, see
           <a href="description" target="_blank">the level description</a>.
         </p>
       </div>