🔀 Merge main to pyml

.github/workflows/clang-tidy-review-post.yml

@@ -41,7 +41,7 @@ jobs:
       # Posts the comments
       - name: Post review comments
         id: post-review
-        uses: ZedThree/clang-tidy-review/post@v0.14.0
+        uses: ZedThree/clang-tidy-review/post@v0.17.0
 
       # If there are any comments, fail the check
       - if: steps.post-review.outputs.total_comments > 0

.github/workflows/clang-tidy-review.yml

@@ -24,7 +24,7 @@ jobs:
           submodules: recursive
 
       - name: Review code with Clang-Tidy
-        uses: ZedThree/clang-tidy-review@v0.14.0
+        uses: ZedThree/clang-tidy-review@v0.17.0
         id: review
         with:
           cmake_command: >
@@ -47,7 +47,7 @@ jobs:
           ignore_case: true
 
       - name: Upload review artifact
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: clang-tidy-review
           path: |

.github/workflows/codeql-analysis.yml

@@ -78,7 +78,7 @@ jobs:
           max-size: 10G
 
       - name: Setup Python
-        uses: actions/setup-python@v4
+        uses: actions/setup-python@v5
         with:
           python-version: '3.9.x'
           cache: 'pip'
@@ -103,7 +103,7 @@ jobs:
 
       # Initializes the CodeQL tools for scanning.
       - name: Initialize CodeQL
-        uses: github/codeql-action/init@v2
+        uses: github/codeql-action/init@v3
         with:
           languages: ${{ matrix.language }}
           config-file: .github/codeql-config.yml
@@ -133,10 +133,10 @@ jobs:
       - if: matrix.language == 'cpp'
         name: Build fiction
         working-directory: ${{github.workspace}}/build
-        run: cmake --build .
+        run: cmake --build . --config ${{matrix.build_type}} -j4
 
       - name: Perform CodeQL Analysis
-        uses: github/codeql-action/analyze@v2
+        uses: github/codeql-action/analyze@v3
         with:
           upload: false
           output: sarif-results
@@ -152,6 +152,6 @@ jobs:
           output: sarif-results/${{ matrix.language }}.sarif
 
       - name: Upload SARIF to GitHub
-        uses: github/codeql-action/upload-sarif@v2
+        uses: github/codeql-action/upload-sarif@v3
         with:
           sarif_file: sarif-results/${{ matrix.language }}.sarif

.github/workflows/coverage.yml

@@ -61,7 +61,7 @@ jobs:
           max-size: 10G
 
       - name: Setup Python
-        uses: actions/setup-python@v4
+        uses: actions/setup-python@v5
         with:
           python-version: '3.9.x'
           cache: 'pip'
@@ -106,12 +106,12 @@ jobs:
 
       - name: Build
         working-directory: ${{github.workspace}}/build
-        run: cmake --build . --config $BUILD_TYPE
+        run: cmake --build . --config $BUILD_TYPE -j4
 
       - name: Test
         working-directory: ${{github.workspace}}/build
 
-        run: ctest -C $BUILD_TYPE --verbose --output-on-failure --parallel 2
+        run: ctest -C $BUILD_TYPE --verbose --output-on-failure --parallel 4
 
       - name: Setup and run lcov
         run: |

.github/workflows/macos.yml

@@ -64,8 +64,9 @@ jobs:
         with:
           submodules: recursive
 
-      # Setup TBB for parallel STL algorithms via Homebrew
-      - name: Setup TBB
+      # Setup TBB for parallel STL algorithms via Homebrew (macOS 11 is no longer supported)
+      - if: matrix.os != 'macos-11'
+        name: Setup TBB
         run: brew install tbb
 
       # Use XCode 13.2 as a workaround because XCode 14.0 seems broken

.github/workflows/ubuntu.yml

@@ -90,7 +90,7 @@ jobs:
           max-size: 10G
 
       - name: Setup Python
-        uses: actions/setup-python@v4
+        uses: actions/setup-python@v5
         with:
           python-version: '3.9.x'
           cache: 'pip'
@@ -136,10 +136,10 @@ jobs:
 
       - name: Build fiction
         working-directory: ${{github.workspace}}/build
-        run: cmake --build .
+        run: cmake --build . --config ${{matrix.build_type}} -j4
 
       - name: Test
         working-directory: ${{github.workspace}}/build
         # Execute tests defined by the CMake configuration.
         # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail
-        run: ctest -C ${{matrix.build_type}} --verbose --output-on-failure --parallel 2
+        run: ctest -C ${{matrix.build_type}} --verbose --output-on-failure --parallel 4

.github/workflows/windows.yml

@@ -97,10 +97,10 @@ jobs:
 
       - name: Build
         working-directory: ${{github.workspace}}\build
-        run: cmake --build . --config ${{matrix.build_type}} -j2
+        run: cmake --build . --config ${{matrix.build_type}} -j4
 
       - name: Test
         working-directory: ${{github.workspace}}\build
         # Execute tests defined by the CMake configuration.
         # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail
-        run: ctest -C ${{matrix.build_type}} --verbose --output-on-failure --parallel 2
+        run: ctest -C ${{matrix.build_type}} --verbose --output-on-failure --parallel 4

README.md

@@ -213,17 +213,18 @@ using
 
 ### Physical Simulation
 
+<img src="docs/_static/sidb_simulation.png" alt="SiDB simulation result" align="right" width="270"/>
+
 When a layout is compiled to the cell level via the application of a technology-dependent gate library, it can be
 simulated using a physical model. Currently, the following simulation algorithms are implemented in *fiction*:
 
 - Silicon Dangling Bonds (SiDBs)
-  - Electrostatic Ground State Simulation
-      - [*QuickExact*](https://arxiv.org/abs/2308.04487)
-      - [*QuickSim*](https://ieeexplore.ieee.org/document/10231266)
-      - [Exhaustive *(ExGS)*](https://open.library.ubc.ca/soa/cIRcle/collections/ubctheses/24/items/1.0392909)
-  - [Critical Temperature Simulation](https://ieeexplore.ieee.org/document/10231259)
-  - [Operational Domain Computation](https://www.cda.cit.tum.de/files/eda/2023_nanoarch_reducing_the_complexity_of_operational_domain_computation_in_silicon_dangling_bond_logic.pdf)
-
+    - Electrostatic Ground State Simulation
+        - [*QuickExact*](https://arxiv.org/abs/2308.04487)
+        - [*QuickSim*](https://ieeexplore.ieee.org/document/10231266)
+        - [Exhaustive *(ExGS)*](https://open.library.ubc.ca/soa/cIRcle/collections/ubctheses/24/items/1.0392909)
+    - [Critical Temperature Simulation](https://ieeexplore.ieee.org/document/10231259)
+    - [Operational Domain Computation](https://www.cda.cit.tum.de/files/eda/2023_nanoarch_reducing_the_complexity_of_operational_domain_computation_in_silicon_dangling_bond_logic.pdf)
 
 ## Clocking Schemes
 
@@ -243,9 +244,9 @@ Built-in schemes are
 |:--------------------------------------------------------:|:------------------------------------------------------------------------:|:---------------------------------------------------------------------------:|
 | <img src="docs/_static/use.png" alt="USE" height="200"/> |         <img src="docs/_static/res.png" alt="RES" height="200"/>         |          <img src="docs/_static/esr.png" alt="ESR" height="200"/>           |
 
-| [CFE](https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cds.2019.0096) |    [BANCS](https://ieeexplore.ieee.org/document/8533251)     |
-|:--------------------------------------------------------------------------------:|:------------------------------------------------------------:|
-|             <img src="docs/_static/cfe.png" alt="CFE" height="200"/>             | <img src="docs/_static/bancs.png" alt="BANCS" height="300"/> |
+| [CFE](https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cds.2019.0096) | [Ripple](https://scholarworks.rit.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=8266&context=theses) |    [BANCS](https://ieeexplore.ieee.org/document/8533251)     |
+|:--------------------------------------------------------------------------------:|:------------------------------------------------------------------------------------------------------------:|:------------------------------------------------------------:|
+|             <img src="docs/_static/cfe.png" alt="CFE" height="200"/>             |                        <img src="docs/_static/ripple.png" alt="Ripple" height="200"/>                        | <img src="docs/_static/bancs.png" alt="BANCS" height="300"/> |
 
 plus the mentioned irregular open clocking that works via a clock map instead of a regular extrapolated cutout.
 
@@ -313,6 +314,18 @@ Cell-level layouts:
 - Bounding box
 - Area usage in nm²
 
+## Benchmark Library
+
+To objectively evaluate and compare software and design automation
+tools, [MNT Bench](https://www.cda.cit.tum.de/mntbench/) provides gate-level
+layouts for various gate libraries and clocking schemes, generated using the latest physical design and
+optimization algorithms, with *fiction* offering the corresponding read and write utilities to generate gate-level
+layouts from gate-level layout files (``.fgl``) and vice versa.
+
+Additionally, the [benchmarks](https://github.com/cda-tum/fiction/tree/main/benchmarks) folder contains the function
+descriptions of frequently used benchmark sets in Verilog format (``.v``) provided
+by [MNT Bench](https://www.cda.cit.tum.de/mntbench/).
+
 # Reference
 
 Since *fiction* is academic software, we would be thankful if you referred to it by citing the following publication:

benchmarks/README.md

@@ -0,0 +1,20 @@
+# Benchmarks
+
+To objectively evaluate and compare software and design automation tools for the physical design of FCN, diverse benchmark sets with function descriptions are needed.
+[MNT Bench](/mntbench/) provides functions from the following benchmark sets in Verilog (``.v``) format:
+
+1. [Trindade16](https://ieeexplore.ieee.org/document/7724048)
+2. [Fontes18](https://ieeexplore.ieee.org/document/8351001)
+3. [ISCAS85](https://www.researchgate.net/publication/273775783_A_neutral_netlist_of_10_combinational_benchmark_circuits_and_a_targeted_translator_in_FORTRAN)
+4. [EPFL](https://www.epfl.ch/labs/lsi/page-102566-en-html/benchmarks/)
+
+For convenience, they are also part of *fiction* to be directly used in experiments or the development of new physical design algorithms, optimizations, and simulators.
+
+# Gate-level Layouts
+
+Gate-level layouts generated with any of the physical design methods implemented in *fiction* can be stored in a human-readable file format (``.fgl``) with the
+correponding [write](https://fiction.readthedocs.io/en/latest/io/physical_simulation.html#technology-independent-gate-level-layouts) function.
+
+[MNT Bench](https://www.cda.cit.tum.de/mntbench/) offers gate-level layouts spanning various gate libraries, clocking schemes, physical
+design algorithms, and optimizations. These layouts can be [read](https://fiction.readthedocs.io/en/latest/io/input.html#gate-level-layouts) with *fiction* and used for testing new
+post-layout optimization algorithms, creating cell-level layouts, or any other use case.

bindings/pyfiction/include/pyfiction/algorithms/physical_design/design_sidb_gates.hpp

@@ -45,7 +45,7 @@ void design_sidb_gates(pybind11::module& m)
     py::class_<fiction::design_sidb_gates_params<Lyt>>(m, "design_sidb_gates_params",
                                                        DOC(fiction_design_sidb_gates_params))
         .def(py::init<>())
-        .def_readwrite("phys_params", &fiction::design_sidb_gates_params<Lyt>::phys_params,
+        .def_readwrite("simulation_parameters", &fiction::design_sidb_gates_params<Lyt>::simulation_parameters,
                        DOC(fiction_design_sidb_gates_params_phys_params))
         .def_readwrite("design_mode", &fiction::design_sidb_gates_params<Lyt>::design_mode,
                        DOC(fiction_design_sidb_gates_params_design_mode))

bindings/pyfiction/include/pyfiction/algorithms/simulation/sidb/critical_temperature.hpp

@@ -60,20 +60,6 @@ inline void critical_temperature(pybind11::module& m)
 {
     namespace py = pybind11;
 
-    /**
-     * Critical temperature mode.
-     */
-    py::enum_<fiction::critical_temperature_params::critical_temperature_mode>(
-        m, "critical_temperature_mode", DOC(fiction_critical_temperature_params_critical_temperature_mode))
-        .value("GATE_BASED_SIMULATION",
-               fiction::critical_temperature_params::critical_temperature_mode::GATE_BASED_SIMULATION,
-               DOC(fiction_critical_temperature_params_critical_temperature_mode_GATE_BASED_SIMULATION))
-        .value("NON_GATE_BASED_SIMULATION",
-               fiction::critical_temperature_params::critical_temperature_mode::NON_GATE_BASED_SIMULATION,
-               DOC(fiction_critical_temperature_params_critical_temperature_mode_NON_GATE_BASED_SIMULATION))
-
-        ;
-
     /**
      * Simulation engine.
      */

bindings/pyfiction/include/pyfiction/algorithms/simulation/sidb/minimum_energy.hpp

@@ -10,6 +10,8 @@
 
 #include <fiction/algorithms/simulation/sidb/minimum_energy.hpp>
 
+#include <vector>
+
 #include <pybind11/pybind11.h>
 #include <pybind11/stl.h>
 
@@ -24,7 +26,11 @@ void minimum_energy(pybind11::module& m)
 {
     using namespace pybind11::literals;
 
-    m.def("minimum_energy", &fiction::minimum_energy<Lyt>, "charge_lyts"_a, DOC(fiction_minimum_energy));
+    m.def(
+        "minimum_energy",
+        [](const std::vector<Lyt>& layouts) -> double
+        { return fiction::minimum_energy(layouts.cbegin(), layouts.cend()); },
+        "layouts"_a, DOC(fiction_minimum_energy));
 }
 
 }  // namespace detail

bindings/pyfiction/test/algorithms/simulation/sidb/test_critical_temperature.py

@@ -29,7 +29,7 @@ def test_perturber_and_DB_pair(self):
     def test_gate_based_simulation(self):
         layout = read_sqd_layout(dir_path + "/../../../resources/hex_21_inputsdbp_xor_v1.sqd", "xor_gate")
         params = critical_temperature_params()
-        params.simulation_parameters.simulation_parameters.base = 2
+        params.simulation_parameters.base = 2
         params.engine = simulation_engine.EXACT
 
         stats = critical_temperature_stats()

cli/CMakeLists.txt

@@ -9,6 +9,26 @@ add_executable(fiction ${SOURCES})
 # Link against the project settings, libfiction and alice
 target_link_libraries(fiction PRIVATE libfiction alice)
 
+# Compile-time decisions on which flows to compile
+
+# Logic synthesis flow
+option(FICTION_LOGIC_SYNTHESIS_FLOW "Enable the logic synthesis flow for the fiction CLI" ON)
+if(FICTION_LOGIC_SYNTHESIS_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_LOGIC_SYNTHESIS_FLOW)
+endif()
+
+# Physical design flow
+option(FICTION_PHYSICAL_DESIGN_FLOW "Enable the physical design flow for the fiction CLI" ON)
+if(FICTION_PHYSICAL_DESIGN_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_PHYSICAL_DESIGN_FLOW)
+endif()
+
+# Physical simulation flow
+option(FICTION_SIMULATION_FLOW "Enable the physical simulation flow for the fiction CLI" ON)
+if(FICTION_SIMULATION_FLOW)
+  target_compile_definitions(fiction PRIVATE FICTION_SIMULATION_FLOW)
+endif()
+
 # Strip the executable if we are in Release mode
 if(CMAKE_BUILD_TYPE STREQUAL "Release")
   if(CMAKE_STRIP)