📝 added documentation for nano papers.

docs/publications.rst

@@ -222,6 +222,44 @@ Furthermore, if you use any of the design automation algorithms, please consider
 
     `Clock number assignment experiment script <https://github.com/cda-tum/fiction/tree/main/experiments/clock_number_assignment>`_
 
+* :ref:`On-the-fly Defect-Aware Design of Circuits <on_the_fly_design>`:
+
+    .. code-block:: tex
+
+        @inproceedings{drewniok2024ontheflydesign,
+          title={{On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic}},
+          author={Drewniok, Jan and Walter, Marcel and Hang Ng, Samuel Sze and Walus, Konrad and Wille, Robert},
+          booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)},
+          pages={30--35},
+          year={2024}
+        }
+
+    `On-the-fly defect-aware design of circuits experiment script <https://github.com/cda-tum/fiction/tree/main/experiments/physical_design_with_on_the_fly_gate_design>`_
+
+* :ref:`Unifying Figures of Merit for Silicon Dangling Bond Logic`:
+
+    .. code-block:: tex
+
+        @inproceedings{drewniok2024figuresofmerit,
+          title={{Unifying Figures of Merit: A Versatile Cost Function for Silicon Dangling Bond Logic}},
+          author={Drewniok, Jan and Walter, Marcel and Hang Ng, Samuel Sze and Walus, Konrad and Wille, Robert},
+          booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)},
+          pages={91--96},
+          year={2024}
+        }
+
+* :ref:`Alternative Silicon Orientations <alternative_hsi_lattices>`:
+
+    .. code-block:: tex
+
+        @inproceedings{ng2024latorientations,
+          title={{Unlocking Flexible Silicon Dangling Bond Logic Designs on Alternative Silicon Orientations}},
+          author={Ng, Samuel Sze Hang and Drewniok, Jan and Walter, Marcel and Retallick, Jacob and Wille, Robert and Walus, Konrad},
+          booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)},
+          pages={57--92},
+          year={2024}
+        }
+
 * :ref:`SiDB Bestagon library <bestagon>`:
 
     .. code-block:: tex

docs/technology/hsi_lattices.rst

@@ -1,3 +1,5 @@
+.. _alternative_hsi_lattices:
+
 H-Si Lattice Orientations
 =========================
 

experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp

@@ -38,6 +38,10 @@
 // This script conducts defect-aware placement and routing with defect-aware on-the-fly SiDB gate design. Thereby, SiDB
 // circuits can be designed in the presence of atomic defects.
 
+// This algorithm was proposed in \"On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic\" by
+// J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in IEEE NANO 2024
+// (https://ieeexplore.ieee.org/abstract/document/10628962).
+
 int main()  // NOLINT
 {
     using gate_lyt = fiction::hex_even_row_gate_clk_lyt;

include/fiction/algorithms/physical_design/determine_clocking.hpp

@@ -404,7 +404,8 @@ class determine_clocking_impl
  * If no valid clock number assignment exists for `lyt`, this function returns `false` and does not modify `lyt`.
  *
  * This algorithm was proposed in \"Ending the Tyranny of the Clock: SAT-based Clock Number Assignment for Field-coupled
- * Nanotechnologies\" by M. Walter, J. Drewniok, and R. Wille in IEEE NANO 2024.
+ * Nanotechnologies\" by M. Walter, J. Drewniok, and R. Wille in IEEE NANO 2024
+ * (https://ieeexplore.ieee.org/abstract/document/10628908).
  *
  * @tparam Lyt Gate-level layout type.
  * @param lyt The gate-level layout to assign clock numbers to.

include/fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp

@@ -164,7 +164,8 @@ class on_the_fly_circuit_design_impl
  * circuit remains functional even in the presence of defects.
  *
  * This methodology is detailed in the paper "On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond
- * Logic" by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024.
+ * Logic" by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024
+ * (https://ieeexplore.ieee.org/abstract/document/10628962).
  *
  * @tparam Ntk The type of the input network.
  * @tparam CellLyt Cell-level layout type.