Initial commit

.gitattributes

@@ -0,0 +1,2 @@
+# Auto detect text files and perform LF normalization
+* text=auto

MIPS处理器约定.txt

@@ -0,0 +1,25 @@
+OPCode
+blez	h6
+bgtz	h7
+bltz	h1
+JALR Jump And Link Register	rd=pc; pc=rs	000000 rs 00000	rd 00000 001001
+
+PCSrc PC+4:0 branch:1 j,jal:2 jr,jalr:3
+RegDst 0:rt 1:rd 2:$ra
+MemtoReg 0:ALUout 1:MEMout
+ALUorRA 0:ALUrslt(ALU计算结果) 1:PC+4(用于jal,jalr) 作为ALUout
+MemWriteDataSource, //0:不转发 1:从WB转发
+
+ALUSrcA 0:busA 1:Shamt
+ALUSrcB 0:busB 1:Imm
+
+busAMUX busBMUX 0:不转发 1:从EXMEM转发 2:从WB转发
+
+寄存器的阻塞与清零
+0:正常顺序执行 1:清零 2:保持
+
+阻塞处置办法
+若第i级之前的指令需要阻塞，则将第1~i-2级后的寄存器保持，i-1级的寄存器清0，PC
+
+BCD控制方法
+向0x40000010中写32位数，[31:12]补0 [11:8]an [7:0]BCDData

README.md

@@ -0,0 +1,2 @@
+# PipelineCPU
+ THU EE 2023-Summer Coursework

src/ALU.v

@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+module ALU (
+    ALUCtrl,
+    sign,
+    in1,
+    in2,
+    out
+);
+
+parameter ADD = 5'h0;
+parameter SUB = 5'h1;
+parameter AND = 5'h2;
+parameter OR = 5'h3;
+parameter XOR = 5'h4;
+parameter NOR = 5'h5;
+parameter SLL = 5'h6;
+parameter SRL = 5'h7;
+parameter SRA = 5'h8;
+parameter SLT = 5'h9;
+
+input [4:0] ALUCtrl;
+input sign;
+input [31:0] in1;
+input [31:0] in2;
+output [31:0] out;
+
+reg [31:0] out;
+
+wire unsigned_lo31_lt;
+wire signed_lt;
+assign unsigned_lo31_lt = (in1[30:0] < in2[30:0]);
+assign signed_lt = (in1[31] ^ in2[31]) ? (in1[31]? 1 : 0) : unsigned_lo31_lt;
+
+always @(*) begin
+    case(ALUCtrl)
+    ADD: out <= in1 + in2;
+    SUB: out <= in1 - in2;
+    AND: out <= in1 & in2;
+    OR: out <= in1 | in2;
+    XOR: out <= in1 ^ in2;
+    NOR: out <= ~(in1 | in2);
+    SLL: out <= in2 << in1[4:0];
+    SRL: out <= in2 >> in1[4:0];
+    SRA: out <= {{32{in2[31]}}, in2} >> in1[4:0];
+    SLT: out <= {31'h00000000, sign ? signed_lt : in1 < in2};
+    default: out <= 0;
+    endcase
+end
+
+endmodule

src/ALUControl.v

@@ -0,0 +1,137 @@
+`timescale 1ns / 1ps
+module ALUControl (
+    input wire [5:0]OpCode,
+    input wire [5:0]Funct,
+    output reg [4:0]ALUCtrl,
+    output reg Sign
+);
+
+parameter ADD = 5'h0;
+parameter SUB = 5'h1;
+parameter AND = 5'h2;
+parameter OR = 5'h3;
+parameter XOR = 5'h4;
+parameter NOR = 5'h5;
+parameter SLL = 5'h6;
+parameter SRL = 5'h7;
+parameter SRA = 5'h8;
+parameter SLT = 5'h9;
+
+always @(*) begin
+    case(OpCode)
+    6'h23: begin
+        ALUCtrl <= ADD;  // lw
+        Sign <= 1;
+    end
+    6'h20: begin
+        ALUCtrl <= ADD;  // load byte(lb)
+        Sign <= 1;
+    end
+    6'h2b: begin
+        ALUCtrl <= ADD;  // sw
+        Sign <= 1;
+    end
+    6'h0f: begin
+        ALUCtrl <= ADD; // lui
+        Sign <= Sign; //don't care
+    end
+    6'h08: begin
+        ALUCtrl <= ADD; //addi
+        Sign <= 1;
+    end
+    6'h09: begin
+        ALUCtrl <= ADD; //addiu
+        Sign <= 0;
+    end
+    6'h0c: begin
+        ALUCtrl <= AND; //andi
+        Sign <= Sign;
+    end
+    6'h0d: begin
+        ALUCtrl <= OR; //ori
+        Sign <= Sign;
+    end
+    6'h0a: begin
+        ALUCtrl <= SLT; //slti
+        Sign <= 1;
+    end
+    6'h0b: begin
+        ALUCtrl <= SLT; //sltiu
+        Sign <= 0;
+    end
+    6'h04: begin
+        ALUCtrl <= SUB; // beq
+        Sign <= Sign; //don't care
+    end
+    default: begin // Opcode = 0
+        case(Funct)
+        6'h20: begin
+            ALUCtrl <= ADD;
+            Sign <= 1;
+        end
+        6'h21: begin
+            ALUCtrl <= ADD;
+            Sign <= 0;
+        end
+        6'h22: begin
+            ALUCtrl <= SUB;
+            Sign <= 1;
+        end
+        6'h23: begin
+            ALUCtrl <= SUB;
+            Sign <= 0;
+        end
+        6'h24: begin
+            ALUCtrl <= AND;
+            Sign <= Sign;
+        end
+        6'h25: begin
+            ALUCtrl <= OR;
+            Sign <= Sign;
+        end
+        6'h26: begin
+            ALUCtrl <= XOR;
+            Sign <= Sign;
+        end
+        6'h27: begin
+            ALUCtrl <= NOR;
+            Sign <= Sign;
+        end
+        6'h00: begin
+            ALUCtrl <= SLL;
+            Sign <= Sign;
+        end
+        6'h02: begin
+            ALUCtrl <= SRL;
+            Sign <= 0;
+        end
+        6'h03: begin
+            ALUCtrl <= SRA;
+            Sign <= 1;
+        end
+        6'h2a: begin
+            ALUCtrl <= SLT;
+            Sign <= 1;
+        end
+        6'h2b: begin
+            ALUCtrl <= SLT;
+            Sign <= 0;
+        end
+        6'h08: begin
+            ALUCtrl <= ADD;  // jr
+            Sign <= Sign;
+        end
+        6'h09: begin
+            ALUCtrl <= ADD;  // jalr
+            Sign <= Sign;
+        end
+        default: begin
+            ALUCtrl <= ALUCtrl;
+            Sign <= Sign;
+        end
+        endcase
+    end
+    endcase    
+end
+
+endmodule

src/CPU.v

@@ -0,0 +1,112 @@
+`timescale 1ns / 1ps
+//To be compeleted
+module CPU(
+    input wire reset, 
+	input wire clk, 
+	input wire [31:0] MemBus_Read_Data,
+	output wire MemRead, 
+	output wire MemWrite,
+	output wire [31:0] MemBus_Address, 
+	output wire [31:0] MemBus_Write_Data
+    );
+
+    wire [1:0]IFIDop;
+    wire [1:0]IDEXop;
+    wire [1:0]EXMEMop;
+
+    wire [1:0]IF_PCSrc;
+    wire [31:0]IF_jPC;
+    wire [31:0]IF_jrPC;
+    wire [31:0]IF_branchPC;
+    wire IF_comp_true;
+    wire [31:0]ID_PCplus4;
+    wire [31:0]ID_Instruction;
+
+    IF IFstage(.reset(reset),.clk(clk),.IFIDop(IFIDop),.IDEXop(IDEXop),.EXMEMop(EXMEMop),
+               .PCSrc(IF_PCSrc),.jPC(IF_jPC),.jrPC(IF_jrPC),.branchPC(IF_branchPC),
+               .comp_true(IF_comp_true),.PC_plus_4(ID_PCplus4),.Instruction(ID_Instruction));
+
+    wire [31:0]EXMEM_ALUout;
+    wire [1:0]ID_compSourceA;
+    wire [1:0]ID_compSourceB;
+    wire [31:0]WB_RegWriteData;
+    wire MEMWB_RegWrite;
+    wire [4:0]MEMWB_RegWriteAddr;
+    wire [31:0]IDEX_PCplus4;
+    wire IDEX_RegWrite;
+    wire IDEX_MemRead;
+    wire [4:0]IDEX_WriteRegAddr;
+    wire IDEX_MemWrite;
+    wire IDEX_MemtoReg;
+    wire IDEX_ALUSrcA;
+    wire IDEX_ALUSrcB;
+    wire [4:0]IDEX_ALUCtrl;
+    wire IDEX_Sign;
+    wire [31:0]IDEX_busA;
+    wire [31:0]IDEX_busB;
+    wire [31:0]IDEX_Imm;
+    wire [4:0]IDEX_Shamt;
+    wire [4:0]IDEX_rs;
+    wire [4:0]IDEX_rt;
+    wire IDEX_ALUorRA;
+    wire [4:0]ID_rs;
+    wire [4:0]ID_rt;
+
+    ID IDstage(.reset(reset),.clk(clk),.IDEXop(IDEXop),.PCplus4(ID_PCplus4),
+               .Instruction(ID_Instruction),.EX_MEM_ALUout(EXMEM_ALUout),
+               .compSourceA(ID_compSourceA),.compSourceB(ID_compSourceB),
+               .RegWriteData(WB_RegWriteData),.WriteAddr(MEMWB_RegWriteAddr),.RegWrite(MEMWB_RegWrite),.jPC(IF_jPC),
+               .jrPC(IF_jrPC),.branchPC(IF_branchPC),.comp_true(IF_comp_true),
+               .PCSrc(IF_PCSrc),.rs(ID_rs),.rt(ID_rt),.IDEX_PCplus4(IDEX_PCplus4),.IDEX_RegWrite(IDEX_RegWrite),
+               .IDEX_MemRead(IDEX_MemRead),.IDEX_WriteRegAddr(IDEX_WriteRegAddr),
+               .IDEX_MemWrite(IDEX_MemWrite),.IDEX_MemtoReg(IDEX_MemtoReg),
+               .IDEX_ALUSrcA(IDEX_ALUSrcA),.IDEX_ALUSrcB(IDEX_ALUSrcB),.IDEX_ALUCtrl(IDEX_ALUCtrl),
+               .IDEX_Sign(IDEX_Sign),.IDEX_busA(IDEX_busA),.IDEX_busB(IDEX_busB),
+               .IDEX_Imm(IDEX_Imm),.IDEX_Shamt(IDEX_Shamt),.IDEX_rs(IDEX_rs),.IDEX_rt(IDEX_rt),
+               .IDEX_ALUorRA(IDEX_ALUorRA));
+
+    wire [1:0]EX_busAMUX;
+    wire [1:0]EX_busBMUX;
+    wire EXMEM_RegWrite;
+    wire [4:0]EXMEM_WriteRegAddr;
+    wire EXMEM_MemtoReg;
+    wire EXMEM_MemWrite;
+    assign MemWrite = EXMEM_MemWrite;
+    wire EXMEM_MemRead;
+    assign MemRead = EXMEM_MemRead;
+    wire [31:0]EXMEM_MemWriteData;
+    wire [4:0]EXMEM_rt;
+    wire MEM_MemWriteDataSource;
+    wire [31:0]MEM_MemReadData;
+    wire [31:0]MEM_RealMemWriteData;
+    //wire MEMWB_RegWrite;
+    //wire [4:0]MEMWB_RegWriteAddr;
+    wire MEMWB_MemtoReg;
+    wire [31:0]MEMWB_MemReadData;
+    wire [31:0]MEMWB_ALUout;
+    assign MemBus_Address = EXMEM_ALUout;
+    assign MemBus_Write_Data = MEM_RealMemWriteData;
+    assign MEM_MemReadData = MemBus_Read_Data;
+
+    EX EXstage(.reset(reset),.clk(clk),.EXMEMop(EXMEMop),.busAMUX(EX_busAMUX),.busBMUX(EX_busBMUX),
+               .PCplus4(IDEX_PCplus4),.RegWrite(IDEX_RegWrite),.MemRead(IDEX_MemRead),.WriteRegAddr(IDEX_WriteRegAddr),
+               .MemWrite(IDEX_MemWrite),.MemtoReg(IDEX_MemtoReg),.ALUorRA(IDEX_ALUorRA),
+               .ALUSrcA(IDEX_ALUSrcA),.ALUSrcB(IDEX_ALUSrcB),.ALUCtrl(IDEX_ALUCtrl),.Sign(IDEX_Sign),
+               .busA(IDEX_busA),.busB(IDEX_busB),.Imm(IDEX_Imm),.Shamt(IDEX_Shamt),.rt(IDEX_rt),.WB_RegWriteData(WB_RegWriteData),
+               .EXMEM_ALUout(EXMEM_ALUout),.EXMEM_RegWrite(EXMEM_RegWrite),.EXMEM_WriteRegAddr(EXMEM_WriteRegAddr),.EXMEM_MemtoReg(EXMEM_MemtoReg),
+               .EXMEM_MemWrite(EXMEM_MemWrite),.EXMEM_MemRead(EXMEM_MemRead),.EXMEM_MemWriteData(EXMEM_MemWriteData),.EXMEM_rt(EXMEM_rt));
+
+    MEM MEMstage(.clk(clk),.reset(reset),.ALUout(EXMEM_ALUout),.RegWrite(EXMEM_RegWrite),.RegWriteAddr(EXMEM_WriteRegAddr),.MemtoReg(EXMEM_MemtoReg),
+                 .MemWriteDataSource(MEM_MemWriteDataSource),.MemWriteData(EXMEM_MemWriteData),.MemWriteDataWB(WB_RegWriteData),.MemReadData(MEM_MemReadData),
+                 .realMemWriteData(MEM_RealMemWriteData),.MEMWB_RegWrite(MEMWB_RegWrite),.MEMWB_RegWriteAddr(MEMWB_RegWriteAddr),.MEMWB_MemtoReg(MEMWB_MemtoReg),
+                 .MEMWB_MemReadData(MEMWB_MemReadData),.MEMWB_ALUout(MEMWB_ALUout));
+
+    WB WBstage(.ALUout(MEMWB_ALUout),.MEMout(MEMWB_MemReadData),.MemtoReg(MEMWB_MemtoReg),.WriteData(WB_RegWriteData));
+
+    FwdAndStall FwdAndStallCtrl(.ID_rs(ID_rs),.ID_rt(ID_rt),.ID_PCSrc(IF_PCSrc),.ID_comp_true(IF_comp_true),.IDEX_RegWrite(IDEX_RegWrite),
+                                .IDEX_RegWriteID(IDEX_WriteRegAddr),.EX_rs(IDEX_rs),.EX_rt(IDEX_rt),
+                                .EX_ALUSrcA(IDEX_ALUSrcA),.EX_ALUSrcB(IDEX_ALUSrcB),.EXMEM_RegWrite(EXMEM_RegWrite),.EXMEM_RegWriteID(EXMEM_WriteRegAddr),
+                                .EXMEM_MemtoReg(EXMEM_MemtoReg),.MEM_rt(EXMEM_rt),.WB_RegWriteID(MEMWB_RegWriteAddr),.WB_RegWrite(MEMWB_RegWrite),
+                                .ID_CompSourceA(ID_compSourceA),.ID_CompSourceB(ID_compSourceB),.EX_busAMUX(EX_busAMUX),.EX_busBMUX(EX_busBMUX),.MEM_MemWriteDataSource(MEM_MemWriteDataSource),
+                                .IFIDop(IFIDop),.IDEXop(IDEXop),.EXMEMop(EXMEMop));
+endmodule

src/Comparer.v

@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+module Comparer(
+    input wire [31:0]busA,
+    input wire [31:0]busB,
+    input wire [2:0]compOp, // 比较方法 0:beq 1:bne 2:blez 3:bgtz 4:bltz
+    output reg comp_true // 比较结果，在对应compOp下为真时返回1，否则返回0
+    );
+
+    always @(*) begin
+        case(compOp)
+        3'd0: comp_true <= busA == busB; //beq
+        3'd1: comp_true <= busA != busB; //bne
+        3'd2: comp_true <= busA[31] | (busA == 32'd0); //blez
+        3'd3: comp_true <= (!busA[31] & (busA[30:0] != 31'd0)); //bgtz
+        default: comp_true <= busA[31]; //bltz
+        endcase
+    end
+endmodule