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Merge branch 'main' into builder-qol
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nathanielnrn committed Feb 5, 2024
2 parents f558c28 + cf710a5 commit f6fd273
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Showing 34 changed files with 286 additions and 220 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/docs.yml
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ name: Docs website
on:
push:
branches:
- master
- main

jobs:
playground:
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2 changes: 1 addition & 1 deletion .github/workflows/rust.yml
Original file line number Diff line number Diff line change
Expand Up @@ -185,7 +185,7 @@ jobs:
- name: Run Python Tests
working-directory: /home/calyx
run: pytest fud/fud/stages/verilator/tests/numeric_types.py
run: pytest calyx-py/test/numeric_types.py

evaluation:
name: Polybench Integration
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36 changes: 18 additions & 18 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ members = [
"tools/data_gen",
"cider-dap",
"fud2",
"fud2/fake",
"fud2/fud-core",
]
exclude = ["site"]

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30 changes: 10 additions & 20 deletions calyx-py/calyx/gen_exp.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,8 @@
)
from calyx.utils import float_to_fixed_point
from math import factorial, log2
from fud.stages.verilator import numeric_types
from calyx.numeric_types import FixedPoint
from calyx.gen_ln import generate_ln

from calyx.builder import (
Builder,
ComponentBuilder,
Expand All @@ -19,7 +18,6 @@
if_with,
invoke,
CellBuilder,
ExprBuilder,
const,
HI,
par,
Expand Down Expand Up @@ -52,7 +50,7 @@ def generate_fp_pow_component(

# groups
with comp.group("init") as init:
pow.in_ = numeric_types.FixedPoint(
pow.in_ = FixedPoint(
"1.0", width, int_width, is_signed=is_signed
).unsigned_integer()
pow.write_en = 1
Expand Down Expand Up @@ -105,14 +103,12 @@ def generate_cells(
comp.const(
"one",
width,
numeric_types.FixedPoint(
"1.0", width, int_width, is_signed=is_signed
).unsigned_integer(),
FixedPoint("1.0", width, int_width, is_signed=is_signed).unsigned_integer(),
)
comp.const(
"e",
width,
numeric_types.FixedPoint(
FixedPoint(
str(float_to_fixed_point(2.7182818284, frac_width)),
width,
int_width,
Expand All @@ -124,7 +120,7 @@ def generate_cells(
comp.const(
"negative_one",
width,
numeric_types.FixedPoint(
FixedPoint(
"-1.0", width, int_width, is_signed=is_signed
).unsigned_integer(),
)
Expand Down Expand Up @@ -168,7 +164,7 @@ def generate_cells(
# reciprocal factorials
for i in range(2, degree + 1):
fixed_point_value = float_to_fixed_point(1.0 / factorial(i), frac_width)
value = numeric_types.FixedPoint(
value = FixedPoint(
str(fixed_point_value), width, int_width, is_signed=is_signed
).unsigned_integer()
comp.const(f"reciprocal_factorial{i}", width, value)
Expand Down Expand Up @@ -540,9 +536,7 @@ def gen_constant_cell(
return comp.const(
name,
width,
numeric_types.FixedPoint(
value, width, int_width, is_signed=is_signed
).unsigned_integer(),
FixedPoint(value, width, int_width, is_signed=is_signed).unsigned_integer(),
)


Expand Down Expand Up @@ -571,16 +565,12 @@ def generate_fp_pow_full(
const_one = comp.const(
"one",
width,
numeric_types.FixedPoint(
"1.0", width, int_width, is_signed=is_signed
).unsigned_integer(),
FixedPoint("1.0", width, int_width, is_signed=is_signed).unsigned_integer(),
)
const_zero = comp.const(
"zero",
width,
numeric_types.FixedPoint(
"0.0", width, int_width, is_signed=is_signed
).unsigned_integer(),
FixedPoint("0.0", width, int_width, is_signed=is_signed).unsigned_integer(),
)
mult = comp.cell(
"mult",
Expand All @@ -597,7 +587,7 @@ def generate_fp_pow_full(
const_neg_one = comp.const(
"neg_one",
width,
numeric_types.FixedPoint(
FixedPoint(
"-1.0", width, int_width, is_signed=is_signed
).unsigned_integer(),
)
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2 changes: 1 addition & 1 deletion calyx-py/calyx/gen_ln.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
Import,
)
from calyx.utils import float_to_fixed_point
from fud.stages.verilator import numeric_types
from calyx import numeric_types
from calyx.gen_msb import gen_msb_calc

from calyx.builder import Builder, ComponentBuilder, CellBuilder, HI, par, invoke
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15 changes: 0 additions & 15 deletions calyx-py/calyx/gen_msb.py
Original file line number Diff line number Diff line change
@@ -1,26 +1,11 @@
from typing import List
from calyx.py_ast import (
Connect,
CompVar,
Cell,
Group,
ConstantPort,
CompPort,
Stdlib,
Component,
ThisPort,
HolePort,
PortDef,
SeqComp,
Enable,
While,
Control,
CombGroup,
)
from calyx.builder import (
Builder,
CellAndGroup,
ComponentBuilder,
const,
HI,
while_with,
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Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,20 @@
from fractions import Fraction
from dataclasses import dataclass
from decimal import Decimal, getcontext
from fud.errors import InvalidNumericType
import math
import logging as log


class InvalidNumericType(Exception):
"""
An error raised when an invalid numeric type is provided.
"""

def __init__(self, msg):
msg = f"""Invalid Numeric Type: {msg}"""
super().__init__(msg)


@dataclass
class NumericType:
"""Interface for a numeric type.
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from random import randint
from fud.stages.verilator.numeric_types import FixedPoint, Bitnum
from fud.errors import InvalidNumericType
from calyx.numeric_types import FixedPoint, Bitnum, InvalidNumericType
from hypothesis import given, strategies as st # type: ignore
import numpy as np
import pytest # type: ignore
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2 changes: 1 addition & 1 deletion docs/lang/multi-component.md
Original file line number Diff line number Diff line change
Expand Up @@ -41,5 +41,5 @@ The component executes the two groups in-order.

To see the output from running this component, run the command:
```
fud e examples/futil/multi-component.futil --to vcd_json
fud e examples/futil/multi-component.futil --to vcd
```
12 changes: 9 additions & 3 deletions docs/running-calyx/fud2.md
Original file line number Diff line number Diff line change
Expand Up @@ -17,13 +17,19 @@ You might then want to do something like ``ln -s `pwd`/target/debug/fud2 ~/.loca
fud2 depends on [Ninja][].
Install it using your OS package manager or by downloading a binary.

Create a configuration file at `~/.config/fud2.toml`, using the path to your checkout of the Calyx git repository:
### Configuration

Run the following command to edit `fud2`'s configuration file (usually `~/.config/fud2.toml`):
```
fud2 edit-config
```

Add the following fields:
```toml
rsrc = ".../calyx/fud2/rsrc"
rsrc = "<path to calyx checkout>/fud2/rsrc"

[calyx]
base = ".../calyx"
base = "<path to calyx checkout>"
```

Now you're ready to use fud2.
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2 changes: 1 addition & 1 deletion frontends/relay/relay_visitor.py
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
Component,
)
from calyx.utils import float_to_fixed_point
from fud.stages.verilator import numeric_types
from calyx import numeric_types
from dahlia_impl import emit_components

calyx_keywords_list = ["input"]
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2 changes: 1 addition & 1 deletion frontends/systolic-lang/convert-mems.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
import argparse
import json
from fud.stages.verilator import numeric_types
from calyx import numeric_types


if __name__ == "__main__":
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2 changes: 1 addition & 1 deletion frontends/systolic-lang/gen_array_component.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#!/usr/bin/env python3

from gen_pe import pe, PE_NAME, BITWIDTH
import calyx.builder as cb
from calyx import builder as cb
from calyx import py_ast
from calyx.utils import bits_needed
from systolic_arg_parser import SystolicConfiguration
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4 changes: 2 additions & 2 deletions frontends/systolic-lang/gen_post_op.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
#!/usr/bin/env python3

import calyx.builder as cb
from calyx import builder as cb
from calyx import py_ast
from gen_array_component import NAME_SCHEME
from gen_pe import BITWIDTH, INTWIDTH, FRACWIDTH
from fud.stages.verilator import numeric_types
from calyx import numeric_types
from calyx.utils import float_to_fixed_point
from systolic_arg_parser import SystolicConfiguration
from calyx.utils import bits_needed
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10 changes: 0 additions & 10 deletions fud/fud/errors.py
Original file line number Diff line number Diff line change
Expand Up @@ -255,16 +255,6 @@ def __init__(self, path):
super().__init__(msg)


class InvalidNumericType(FudError):
"""
An error raised when an invalid numeric type is provided.
"""

def __init__(self, msg):
msg = f"""Invalid Numeric Type: {msg}"""
super().__init__(msg)


class Malformed(FudError):
"""
An error raised when the input to a stage is malformed in some manner.
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20 changes: 9 additions & 11 deletions fud/fud/stages/interpreter.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,7 @@
from pathlib import Path
import simplejson as sjson
import numpy as np
from fud.stages.verilator.numeric_types import FixedPoint, Bitnum
from fud.errors import InvalidNumericType
from calyx.numeric_types import FixedPoint, Bitnum, InvalidNumericType
from fud.stages.verilator.json_to_dat import parse_fp_widths, float_to_fixed
from fud.utils import shell, TmpDir, unwrap_or, transparent_shell
from fud import config as cfg
Expand Down Expand Up @@ -88,8 +87,9 @@ def _is_data_converter(self):

def _define_steps(self, input_data, builder, config):
script = config["stages", self.name, "exec"]
data_path_exists: bool = (config["stages", "verilog", "data"] or
config.get(["stages", "mrxl", "data"]))
data_path_exists: bool = config["stages", "verilog", "data"] or config.get(
["stages", "mrxl", "data"]
)

cmd = [
script,
Expand Down Expand Up @@ -118,7 +118,9 @@ def mktmp() -> SourceType.Directory:
"""
return TmpDir()

@builder.step(description="Dynamically retrieve the value of stages.verilog.data")
@builder.step(
description="Dynamically retrieve the value of stages.verilog.data"
)
def get_verilog_data() -> SourceType.Path:
data_path = config.get(["stages", "verilog", "data"])
path = Path(data_path) if data_path else None
Expand Down Expand Up @@ -197,9 +199,7 @@ def parse_output(
data_path = get_verilog_data()

if data_path_exists:
convert_json_to_interp_json(
tmpdir, data_path
)
convert_json_to_interp_json(tmpdir, data_path)

if self._is_data_converter():
if data_path_exists:
Expand All @@ -213,9 +213,7 @@ def parse_output(
result = interpret(input_data, tmpdir)

if "--raw" in cmd:
return parse_output(
result, data_path, tmpdir
)
return parse_output(result, data_path, tmpdir)
else:
return result

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4 changes: 2 additions & 2 deletions fud/fud/stages/verilator/json_to_dat.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
import simplejson as sjson
import numpy as np
from .numeric_types import FixedPoint, Bitnum
from calyx.numeric_types import FixedPoint, Bitnum, InvalidNumericType
from pathlib import Path
from fud.errors import InvalidNumericType, Malformed
from fud.errors import Malformed
import logging as log


Expand Down
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