Add stallable primitives (#1935)

calyx-stdlib/src/primitives.rs

@@ -25,18 +25,20 @@ load_prims! { MATH, "math.futil", "math.sv" }
 load_prims! { COMB_MEMORIES, "memories/comb.futil", "memories/comb.sv" }
 load_prims! { SEQ_MEMORIES, "memories/seq.futil", "memories/seq.sv" }
 load_prims! { PIPELINED, "pipelined.futil", "pipelined.sv" }
+load_prims! { STALLABLE, "stallable.futil", "stallable.sv" }
 load_prims! { SYNC, "sync.futil", "sync.sv" }
 
 /// The core primitive in the compiler
 pub const COMPILE_LIB: (&str, &str) =
     ("compile.futil", include_str!("../primitives/compile.futil"));
 
-pub const KNOWN_LIBS: [(&str, [(&str, &str); 2]); 7] = [
+pub const KNOWN_LIBS: [(&str, [(&str, &str); 2]); 8] = [
     ("core", CORE),
     ("binary_operators", BINARY_OPERATORS),
     ("math", MATH),
     ("comb_memories", COMB_MEMORIES),
     ("seq_memories", SEQ_MEMORIES),
     ("pipelined", PIPELINED),
+    ("stallable", STALLABLE),
     ("sync", SYNC),
 ];

primitives/stallable.futil

@@ -0,0 +1,14 @@
+extern "stallable.sv" {
+    // A latency-sensitive multiplier that takes 4 cycles to compute its result.
+    // If stall is set to a value of 1, the multiplier will stall until the value is
+    // set back to 0.
+    static<4> primitive stallable_mult[WIDTH] (
+        @clk clk: 1,
+        @reset reset: 1,
+        stall: 1,
+        left: WIDTH,
+        right: WIDTH
+    ) -> (
+        out: WIDTH
+    );
+}

primitives/stallable.sv

@@ -0,0 +1,35 @@
+module stallable_mult #(
+    parameter WIDTH = 32
+) (
+    input wire clk,
+    input wire reset,
+    input wire stall,
+    // inputs
+    input wire [WIDTH-1:0] left,
+    input wire [WIDTH-1:0] right,
+    // The input has been committed
+    output wire [WIDTH-1:0] out
+);
+
+logic [WIDTH-1:0] lt, rt, buff0, buff1, buff2, tmp_prod;
+
+assign out = buff2;
+assign tmp_prod = lt * rt;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        lt <= 0;
+        rt <= 0;
+        buff0 <= 0;
+        buff1 <= 0;
+        buff2 <= 0;
+    end else if (!stall) begin
+        lt <= left;
+        rt <= right;
+        buff0 <= tmp_prod;
+        buff1 <= buff0;
+        buff2 <= buff1;
+    end
+end
+
+endmodule