allowed fsm representation in component

calyxir · Nov 4, 2024 · e9ea8dd · e9ea8dd
1 parent f62909c
commit e9ea8dd
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Showing 3 changed files with 35 additions and 13 deletions.
diff --git a/calyx-ir/src/builder.rs b/calyx-ir/src/builder.rs
@@ -75,8 +75,27 @@ impl<'a> Builder<'a> {
             "Cannot construct group with empty name prefix"
         );
         let name = self.component.generate_name(prefix);
+
+        // Construct a new FSM
         let fsm = ir::rrc(ir::FSM::new(name));
 
+        // Fill in the ports of the FSM with default wires
+
+        // Add default holes to the group.
+        // for (name, width) in &[("go", 1), ("done", 1)] {
+        //     let hole = ir::rrc(ir::Port {
+        //         name: ir::Id::from(*name),
+        //         width: *width,
+        //         direction: ir::Direction::Inout,
+        //         parent: ir::PortParent::Group(WRC::from::<ir::FSM>(&fsm)),
+        //         attributes: ir::Attributes::default(),
+        //     });
+        //     fsm.borrow_mut().wires.push(hole);
+        // }
+
+        // Add the group to the component.
+        self.component.get_fsms_mut().add(Rc::clone(&fsm));
+
         fsm
     }
 

diff --git a/calyx-ir/src/component.rs b/calyx-ir/src/component.rs
@@ -1,7 +1,7 @@
 use super::{
     Assignment, Attribute, Attributes, BoolAttr, Builder, Cell, CellType,
     CombGroup, Control, Direction, GetName, Group, Id, NumAttr, PortDef,
-    StaticGroup, RRC,
+    StaticGroup, FSM, RRC,
 };
 use crate::guard::StaticTiming;
 use crate::Nothing;
@@ -37,6 +37,8 @@ pub struct Component {
     pub cells: IdList<Cell>,
     /// Groups of assignment wires.
     pub groups: IdList<Group>,
+    /// FSMs generated during compilation.
+    pub fsms: IdList<FSM>,
     /// Groups of assignment wires
     pub static_groups: IdList<StaticGroup>,
     /// Groups of assignment wires.
@@ -131,6 +133,7 @@ impl Component {
             signature: this_sig,
             cells: IdList::default(),
             groups: IdList::default(),
+            fsms: IdList::default(),
             static_groups: IdList::default(),
             comb_groups: IdList::default(),
             continuous_assignments: vec![],
@@ -163,6 +166,10 @@ impl Component {
         &mut self.groups
     }
 
+    pub fn get_fsms_mut(&mut self) -> &mut IdList<FSM> {
+        &mut self.fsms
+    }
+
     /// gets the component's groups
     pub fn get_static_groups_mut(&mut self) -> &mut IdList<StaticGroup> {
         &mut self.static_groups

diff --git a/calyx-opt/src/passes/dyn_fsm_allocation.rs b/calyx-opt/src/passes/dyn_fsm_allocation.rs
@@ -395,7 +395,6 @@ impl<'b, 'a> Schedule<'b, 'a> {
 
     fn realize_fsm(self, dump_fsm: bool) -> RRC<ir::FSM> {
         ir::rrc(ir::FSM::new(Id::new("fsm")))
-
     }
 }
 
@@ -448,7 +447,7 @@ impl Schedule<'_, '_> {
             );
 
             self.fsm_enables.entry(cur_state).or_default().extend(en_go);
-            
+
             // Enable FSM to be triggered by states besides the most recent
             if early_transitions || has_fast_guarantee {
                 for (st, g) in &prev_states {
@@ -963,23 +962,20 @@ impl Visitor for DynamicFSMAllocation {
     }
 
     fn finish_seq(
-            &mut self,
-            s: &mut calyx_ir::Seq,
-            comp: &mut calyx_ir::Component,
-            sigs: &LibrarySignatures,
-            _comps: &[calyx_ir::Component],
-        ) -> VisResult {
-
+        &mut self,
+        s: &mut calyx_ir::Seq,
+        comp: &mut calyx_ir::Component,
+        sigs: &LibrarySignatures,
+        _comps: &[calyx_ir::Component],
+    ) -> VisResult {
         if !s.attributes.has(ir::BoolAttr::NewFSM) {
-           return Ok(Action::Continue)
+            return Ok(Action::Continue);
         }
 
         let mut builder = ir::Builder::new(comp, sigs);
         let mut sch = Schedule::from(&mut builder);
         sch.calculate_states_seq(s, self.early_transitions)?;
 
-
-
         Ok(Action::Continue)
     }
 }