[Cider 2.0] Basic Simulation flow (#1912)

* clippy lint

* debug printing

* misc nonsense

* checkpoint

* add run program

* rename the stdmem impls

* move the get_next for control points into two separate non-internal functions

* some light documentation and renaming

* add an assert

* add some dinky placeholder printing for internal state

* fix some issues with the memories and move serialization

* set the go ports appropriately

* clean up warnings

interp/src/debugger/cidr.rs

@@ -11,7 +11,7 @@ use crate::interpreter::{ComponentInterpreter, ConstCell, Interpreter};
 use crate::structures::names::{CompGroupName, ComponentQualifiedInstanceName};
 use crate::structures::state_views::StateView;
 use crate::utils::AsRaw;
-use crate::{interpreter_ir as iir, primitives::Serializable};
+use crate::{interpreter_ir as iir, serialization::Serializable};
 
 use calyx_ir::{self as ir, Id, RRC};
 

interp/src/flatten/flat_ir/base.rs

@@ -274,12 +274,21 @@ impl From<AssignmentIdx> for AssignmentWinner {
     }
 }
 
-#[derive(Debug, Clone, PartialEq)]
+#[derive(Clone, PartialEq)]
 pub struct AssignedValue {
     val: Value,
     winner: AssignmentWinner,
 }
 
+impl std::fmt::Debug for AssignedValue {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        f.debug_struct("AssignedValue")
+            .field("val", &format!("{}", &self.val))
+            .field("winner", &self.winner)
+            .finish()
+    }
+}
+
 impl std::fmt::Display for AssignedValue {
     // TODO: replace with something more reasonable
     fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
@@ -342,7 +351,7 @@ impl AssignedValue {
     }
 }
 
-#[derive(Debug, Clone)]
+#[derive(Debug, Clone, Default)]
 /// A wrapper struct around an option of an [AssignedValue]
 pub struct PortValue(Option<AssignedValue>);
 
@@ -398,6 +407,12 @@ impl PortValue {
     pub fn new_implicit(val: Value) -> Self {
         Self(Some(AssignedValue::implicit_value(val)))
     }
+
+    /// Sets the value to undefined and returns the former value if present.
+    /// This is equivalent to [Option::take]
+    pub fn set_undef(&mut self) -> Option<AssignedValue> {
+        self.0.take()
+    }
 }
 
 impl From<Option<AssignedValue>> for PortValue {
@@ -412,6 +427,12 @@ impl From<AssignedValue> for PortValue {
     }
 }
 
+impl From<PortValue> for Option<AssignedValue> {
+    fn from(value: PortValue) -> Self {
+        value.0
+    }
+}
+
 /// A global index for standard groups in the IR
 #[derive(Debug, Eq, Copy, Clone, PartialEq, Hash, PartialOrd, Ord)]
 pub struct GroupIdx(u32);

interp/src/flatten/primitives/builder.rs

@@ -106,7 +106,7 @@ pub fn build_primitive(
             idx_size: _,
         } => match mem_type {
             MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(StdMemD1::new(base_port, *width, false, *size as usize))
+            MemType::Std => Box::new(CombMemD1::new(base_port, *width, false, *size as usize))
         },
         CellPrototype::MemD2 {
             mem_type,
@@ -117,7 +117,7 @@ pub fn build_primitive(
             d1_idx_size: _,
         } => match mem_type {
             MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(StdMemD2::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize))),
+            MemType::Std => Box::new(CombMemD2::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize))),
         },
         CellPrototype::MemD3 {
             mem_type,
@@ -130,7 +130,7 @@ pub fn build_primitive(
             d2_idx_size: _,
         }  => match mem_type {
             MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(StdMemD3::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize))),
+            MemType::Std => Box::new(CombMemD3::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize))),
         },
         CellPrototype::MemD4 {
             mem_type,
@@ -145,7 +145,7 @@ pub fn build_primitive(
             d3_idx_size: _,
         }=> match mem_type {
             MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(StdMemD4::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize, *d3_size as usize))),
+            MemType::Std => Box::new(CombMemD4::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize, *d3_size as usize))),
         },
         CellPrototype::Unknown(_, _) => todo!(),
     }

interp/src/flatten/primitives/combinational.rs

@@ -3,7 +3,6 @@ use std::ops::Not;
 use bitvec::vec::BitVec;
 
 use crate::{
-    errors::InterpreterResult,
     flatten::{
         flat_ir::prelude::{AssignedValue, GlobalPortIdx, PortValue},
         primitives::{
@@ -84,13 +83,6 @@ impl Primitive for StdMux {
         }
     }
 
-    fn reset(&mut self, port_map: &mut PortMap) -> InterpreterResult<()> {
-        ports![&self.base; out: Self::OUT];
-        port_map.write_undef_unchecked(out);
-
-        Ok(())
-    }
-
     fn has_stateful(&self) -> bool {
         false
     }

interp/src/flatten/primitives/macros.rs

@@ -102,10 +102,6 @@ macro_rules! comb_primitive {
                 false
             }
 
-            fn reset(&mut self, map:&mut $crate::flatten::structures::environment::PortMap) -> $crate::errors::InterpreterResult<()> {
-                self.exec_comb(map)?;
-                Ok(())
-            }
         }
     };
 

interp/src/flatten/primitives/prim_trait.rs

@@ -2,7 +2,7 @@ use crate::{
     debugger::PrintCode,
     errors::InterpreterResult,
     flatten::{flat_ir::base::GlobalPortIdx, structures::environment::PortMap},
-    primitives::Serializable,
+    serialization::Serializable,
     values::Value,
 };
 
@@ -30,6 +30,7 @@ impl From<(Value, GlobalPortIdx)> for AssignResult {
 }
 
 /// An enum used to denote whether or not committed updates changed the state
+#[derive(Debug)]
 pub enum UpdateStatus {
     Unchanged,
     Changed,
@@ -50,7 +51,7 @@ impl UpdateStatus {
     /// If the status is unchanged and other is changed, updates the status of
     /// self to changed, otherwise does nothing
     pub fn update(&mut self, other: Self) {
-        if !self.is_changed() && other.is_changed() {
+        if !self.as_bool() && other.as_bool() {
             *self = UpdateStatus::Changed;
         }
     }
@@ -60,7 +61,7 @@ impl UpdateStatus {
     ///
     /// [`Changed`]: UpdateStatus::Changed
     #[must_use]
-    pub fn is_changed(&self) -> bool {
+    pub fn as_bool(&self) -> bool {
         matches!(self, Self::Changed)
     }
 }
@@ -69,7 +70,7 @@ impl std::ops::BitOr for UpdateStatus {
     type Output = Self;
 
     fn bitor(self, rhs: Self) -> Self::Output {
-        if self.is_changed() || rhs.is_changed() {
+        if self.as_bool() || rhs.as_bool() {
             UpdateStatus::Changed
         } else {
             UpdateStatus::Unchanged
@@ -81,7 +82,7 @@ impl std::ops::BitOr for &UpdateStatus {
     type Output = UpdateStatus;
 
     fn bitor(self, rhs: Self) -> Self::Output {
-        if self.is_changed() || rhs.is_changed() {
+        if self.as_bool() || rhs.as_bool() {
             UpdateStatus::Changed
         } else {
             UpdateStatus::Unchanged
@@ -106,10 +107,6 @@ pub trait Primitive {
         Ok(UpdateStatus::Unchanged)
     }
 
-    fn reset(&mut self, _port_map: &mut PortMap) -> InterpreterResult<()> {
-        Ok(())
-    }
-
     fn has_comb(&self) -> bool {
         true
     }