[Calyx-FIRRTL] Initialize output ports (#1944)

* First pass fix at setting output ports that are never used to invalid * Fix clippy errors * Quick debugging of port hack * Initialize output ports for FIRRTL and fix tests * Fix clippy error
calyxir · Mar 3, 2024 · 9311f5f · 9311f5f
1 parent f99a966
commit 9311f5f
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Showing 9 changed files with 49 additions and 16 deletions.
diff --git a/calyx-backend/src/firrtl.rs b/calyx-backend/src/firrtl.rs
@@ -7,6 +7,7 @@ use crate::{traits::Backend, VerilogBackend};
 use calyx_ir::{self as ir, Binding, RRC};
 use calyx_utils::{CalyxResult, Id, OutputFile};
 use ir::Port;
+use std::cell::RefCell;
 use std::collections::HashSet;
 use std::io;
 
@@ -82,6 +83,8 @@ fn emit_component<F: io::Write>(
     comp: &ir::Component,
     f: &mut F,
 ) -> io::Result<()> {
+    let mut dst_set: HashSet<ir::Canonical> = HashSet::new();
+
     writeln!(f, "{}module {}:", SPACING, comp.name)?;
 
     // Inputs and Outputs
@@ -91,6 +94,15 @@ fn emit_component<F: io::Write>(
         emit_port(port, true, f)?;
     }
 
+    // write invalid statements for all output ports.
+    for port_ref in sig.ports.iter() {
+        let port = port_ref.as_ref();
+        if port.borrow().direction == calyx_frontend::Direction::Input {
+            write_invalid_initialization(port, f)?;
+            dst_set.insert(port.borrow().canonical());
+        }
+    }
+
     // Add a COMPONENT START: <name> anchor before any code in the component
     writeln!(f, "{}; COMPONENT START: {}", SPACING.repeat(2), comp.name)?;
 
@@ -118,7 +130,6 @@ fn emit_component<F: io::Write>(
         }
     }
 
-    let mut dst_set: HashSet<ir::Canonical> = HashSet::new();
     // Emit assignments
     for asgn in &comp.continuous_assignments {
         match asgn.guard.as_ref() {
@@ -293,7 +304,7 @@ fn get_port_string(port: &calyx_ir::Port, is_dst: bool) -> String {
 
 // variables that get set in assignments should get initialized to avoid the FIRRTL compiler from erroring.
 fn write_invalid_initialization<F: io::Write>(
-    port: &RRC<ir::Port>,
+    port: &RefCell<ir::Port>,
     f: &mut F,
 ) -> io::Result<()> {
     let default_initialization_str = "; default initialization";

diff --git a/tests/backend/firrtl/and-or-not-guard.expect b/tests/backend/firrtl/and-or-not-guard.expect
@@ -9,10 +9,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
-        ; COMPONENT START: main
-        done <= UInt(1)
         out is invalid ; default initialization
         out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
+        ; COMPONENT START: main
+        done <= UInt(1)
         when and(or(not(cond), cond2), cond3):
             out <= in
         ; COMPONENT END: main

diff --git a/tests/backend/firrtl/basic-cell.expect b/tests/backend/firrtl/basic-cell.expect
@@ -12,6 +12,10 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
+        out is invalid ; default initialization
+        out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
         ; COMPONENT START: identity
         done <= UInt(1)
         out <= in
@@ -22,12 +26,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
+        done is invalid ; default initialization
+        done <= UInt(0)
         ; COMPONENT START: main
         inst id of identity
         inst invoke0_go of std_wire_1
         inst invoke0_done of std_wire_1
-        done is invalid ; default initialization
-        done <= UInt(0)
         when invoke0_done.out:
             done <= UInt(1)
         id.clk <= clk

diff --git a/tests/backend/firrtl/basic-guard.expect b/tests/backend/firrtl/basic-guard.expect
@@ -7,10 +7,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
-        ; COMPONENT START: main
-        done <= UInt(1)
         out is invalid ; default initialization
         out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
+        ; COMPONENT START: main
+        done <= UInt(1)
         when cond:
             out <= in
         ; COMPONENT END: main

diff --git a/tests/backend/firrtl/basic-program.expect b/tests/backend/firrtl/basic-program.expect
@@ -6,6 +6,10 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
+        out is invalid ; default initialization
+        out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
         ; COMPONENT START: main
         done <= UInt(1)
         out <= in

diff --git a/tests/backend/firrtl/comparison-guard.expect b/tests/backend/firrtl/comparison-guard.expect
@@ -9,10 +9,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
-        ; COMPONENT START: main
-        done <= UInt(1)
         out is invalid ; default initialization
         out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
+        ; COMPONENT START: main
+        done <= UInt(1)
         when and(leq(var, var2), cond3):
             out <= in
         ; COMPONENT END: main

diff --git a/tests/backend/firrtl/or-guard.expect b/tests/backend/firrtl/or-guard.expect
@@ -8,10 +8,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
-        ; COMPONENT START: main
-        done <= UInt(1)
         out is invalid ; default initialization
         out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
+        ; COMPONENT START: main
+        done <= UInt(1)
         when or(cond, cond2):
             out <= in
         ; COMPONENT END: main

diff --git a/tests/backend/firrtl/primitive-cells.expect b/tests/backend/firrtl/primitive-cells.expect
@@ -19,6 +19,10 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
+        out is invalid ; default initialization
+        out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
         ; COMPONENT START: plus_one
         inst add of std_add_32
         done <= UInt(1)
@@ -32,12 +36,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
+        done is invalid ; default initialization
+        done <= UInt(0)
         ; COMPONENT START: main
         inst po of plus_one
         inst invoke0_go of std_wire_1
         inst invoke0_done of std_wire_1
-        done is invalid ; default initialization
-        done <= UInt(0)
         when invoke0_done.out:
             done <= UInt(1)
         invoke0_go.in <= go

diff --git a/tests/backend/firrtl/two-or-guards.expect b/tests/backend/firrtl/two-or-guards.expect
@@ -10,10 +10,12 @@ circuit main:
         input clk: Clock
         input reset: UInt<1>
         output done: UInt<1>
-        ; COMPONENT START: main
-        done <= UInt(1)
         out is invalid ; default initialization
         out <= UInt(0)
+        done is invalid ; default initialization
+        done <= UInt(0)
+        ; COMPONENT START: main
+        done <= UInt(1)
         when or(cond, cond2):
             out <= in
         when or(cond2, cond3):