fix borrow error

calyxir · Feb 5, 2024 · 7bf4aad · 7bf4aad
1 parent f076408
commit 7bf4aad
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Showing 3 changed files with 9 additions and 7 deletions.
diff --git a/calyx-ir/src/from_ast.rs b/calyx-ir/src/from_ast.rs
@@ -51,7 +51,7 @@ fn get_comp_latency(
                     });
                 // Annoying thing we have to do bc NonZeroU64.
                 match interval_value {
-                    Some(lat) => Ok(Some(NonZeroU64::new(lat)).unwrap()),
+                    Some(lat) => Ok(NonZeroU64::new(lat)),
                     None => Ok(None),
                 }
             }
@@ -71,7 +71,7 @@ fn get_comp_latency(
                     });
                 // Annoying thing we have to do bc NonZeroU64.
                 match interval_value {
-                    Some(lat) => Ok(Some(NonZeroU64::new(lat)).unwrap()),
+                    Some(lat) => Ok(NonZeroU64::new(lat)),
                     None => Ok(None),
                 }
             }

diff --git a/calyx-opt/src/analysis/inference_analysis.rs b/calyx-opt/src/analysis/inference_analysis.rs
@@ -101,10 +101,12 @@ impl From<&ir::Cell> for GoDone {
                     Some(st) => Some(st),
                     None => port.attributes.get(ir::NumAttr::Promotable),
                 };
-                if st.is_some() {
+                if let Some(static_latency) = st {
                     return done_ports
                         .get(&port.attributes.get(ir::NumAttr::Go))
-                        .map(|done_port| (port.name, *done_port, st.unwrap()));
+                        .map(|done_port| {
+                            (port.name, *done_port, static_latency)
+                        });
                 }
                 None
             })

diff --git a/calyx-opt/src/passes/compile_static_interface.rs b/calyx-opt/src/passes/compile_static_interface.rs
@@ -210,8 +210,8 @@ impl CompileStaticInterface {
         let go_guard = guard!(comp_sig["go"]);
         let not_go_guard = !guard!(comp_sig["go"]);
         let first_state_guard = guard!(fsm["out"] == first_state["out"]);
-        let signal_on_guard = guard!(sig_reg["out"]);
-        let comp_done_guard = first_state_guard & signal_on_guard;
+        let comp_done_guard =
+            guard!(fsm["out"] == first_state["out"]) & guard!(sig_reg["out"]);
         let assigns = build_assignments!(builder;
           // only set sig_reg when fsm == 0
           sig_reg["write_en"] = first_state_guard ? one["out"];
@@ -237,7 +237,7 @@ impl CompileStaticInterface {
           let zero = constant(0, 1);
         );
         let go_guard = guard!(comp_sig["go"]);
-        let not_go = !go_guard;
+        let not_go = !guard!(comp_sig["go"]);
         let signal_on_guard = guard!(sig_reg["out"]);
         let assigns = build_assignments!(builder;
           // comp.done is just whatever comp.go was on the previous cycle.