Merge branch 'main' into piezo-doc

.gitignore

@@ -44,6 +44,9 @@ tests/xilinx/cocotb/**/hdl
 sim_build/
 results.xml
 
+# Ignore .fud2 cache
+.fud2/
+
 
 !cider-dap/calyxDebug/package.json
 !cider-dap/calyxDebug/tsconfig.json

Cargo.toml

@@ -11,6 +11,8 @@ members = [
     "web/rust",
     "tools/data_gen",
     "cider-dap",
+    "fud2",
+    "fud2/fake",
 ]
 exclude = ["site"]
 
@@ -43,6 +45,7 @@ pest = "2"
 pest_derive = "2"
 pest_consume = "1"
 argh = "0.1"
+anyhow = "1"
 calyx-utils = { path = "calyx-utils", version = "0.6.1" }
 calyx-ir = { path = "calyx-ir", version = "0.6.1" }
 calyx-frontend = { path = "calyx-frontend", version = "0.6.1" }
@@ -54,6 +57,12 @@ version = "0.6"
 default-features = false
 features = ["matrix_graph"]
 
+[workspace.dependencies.env_logger]
+version = "0.9.0"
+features = ["termcolor", "atty"]
+default-features = false
+
+
 # =========== Package configuration ===========
 
 [package]
@@ -89,6 +98,7 @@ itertools.workspace = true
 log.workspace = true
 serde.workspace = true
 argh.workspace = true
+env_logger.workspace = true
 
 calyx-utils.workspace = true
 calyx-ir.workspace = true
@@ -99,11 +109,6 @@ calyx-opt.workspace = true
 workspace = true
 features = ["mlir", "resources", "xilinx"]
 
-[dependencies.env_logger]
-version = "0.9.0"
-features = ["termcolor", "atty"]
-default-features = false
-
 [profile.release]
 lto = "thin"
 

calyx-backend/src/firrtl.rs

@@ -36,30 +36,8 @@ impl Backend for FirrtlBackend {
     fn emit(ctx: &ir::Context, file: &mut OutputFile) -> CalyxResult<()> {
         let out = &mut file.get_write();
         writeln!(out, "circuit {}:", ctx.entrypoint)?;
-        // Pass to output any necessary extmodule statements (for primitive calls)
-        let mut extmodule_set: HashSet<String> = HashSet::new();
-        for comp in &ctx.components {
-            for cell in comp.cells.iter() {
-                let cell_borrowed = cell.as_ref().borrow();
-                if let ir::CellType::Primitive {
-                    name,
-                    param_binding,
-                    ..
-                } = &cell_borrowed.prototype
-                {
-                    let curr_module_name =
-                        get_primitive_module_name(name, param_binding);
-                    if extmodule_set.insert(curr_module_name.clone()) {
-                        emit_primitive_extmodule(
-                            cell.borrow().ports(),
-                            &curr_module_name,
-                            name,
-                            param_binding,
-                            out,
-                        )?;
-                    }
-                };
-            }
+        if ctx.bc.emit_primitive_extmodules {
+            emit_extmodules(ctx, out)?;
         }
         for comp in ctx.components.iter() {
             emit_component(comp, out)?
@@ -68,6 +46,37 @@ impl Backend for FirrtlBackend {
     }
 }
 
+fn emit_extmodules<F: io::Write>(
+    ctx: &ir::Context,
+    out: &mut F,
+) -> Result<(), calyx_utils::Error> {
+    let mut extmodule_set: HashSet<String> = HashSet::new();
+    for comp in &ctx.components {
+        for cell in comp.cells.iter() {
+            let cell_borrowed = cell.as_ref().borrow();
+            if let ir::CellType::Primitive {
+                name,
+                param_binding,
+                ..
+            } = &cell_borrowed.prototype
+            {
+                let curr_module_name =
+                    get_primitive_module_name(name, param_binding);
+                if extmodule_set.insert(curr_module_name.clone()) {
+                    emit_primitive_extmodule(
+                        cell.borrow().ports(),
+                        &curr_module_name,
+                        name,
+                        param_binding,
+                        out,
+                    )?;
+                }
+            };
+        }
+    }
+    Ok(())
+}
+
 // TODO: Ask about the other backend configurations in verilog.rs and see if I need any of it
 fn emit_component<F: io::Write>(
     comp: &ir::Component,

calyx-frontend/src/common.rs

@@ -45,7 +45,7 @@ impl Primitive {
     ) -> CalyxResult<(SmallVec<[(Id, u64); 5]>, Vec<PortDef<u64>>)> {
         if self.params.len() != parameters.len() {
             let msg = format!(
-               "Invalid parameter binding for primitive `{}`. Requires {} parameters but provided with {}.",
+               "primitive `{}` requires {} parameters but instantiation provides {} parameters",
                self.name.clone(),
                self.params.len(),
                parameters.len(),