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[Cider | Fud2 stage] Make sim.data optional for the Cider fud2 flow (
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…#2323)

A quick patch for the `fud2` flow which makes it possible to run without
supplying a `sim.data` value which would otherwise block things. This
hopefully makes testing small programs more straightforward as it no
longer requires generating an empty data file or using direct
invocations of the tools.
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EclecticGriffin authored Oct 31, 2024
1 parent b084974 commit 1f31905
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Showing 10 changed files with 96 additions and 120 deletions.
54 changes: 36 additions & 18 deletions fud2/scripts/cider.rhai
Original file line number Diff line number Diff line change
Expand Up @@ -16,33 +16,50 @@ fn cider_setup(e) {
"cider-converter.exe",
"$calyx-base/target/debug/cider-data-converter",
);
e.config_var_or("converter-flags", "cider.converter-flags", "");
e.config_var_or("cider-flags", "cider.flags", "");

let has_data = !e.config_or("sim.data", "").is_empty();

if has_data {
e.var_("data", "--data data.dump");

// copied from rtl_sim.rhai, we only want to do this when the sim.data
// flag is present
let data_name = e.config_val("sim.data");
let data_path = e.external_path(data_name);
e.var_("sim_data", data_path);
} else {
e.var_("data", "")
}

e.rule(
"run-cider-debug",
"$cider-exe -l $calyx-base --data data.dump $cider-flags $in debug || true",
"$cider-exe -l $calyx-base $data $cider-flags $in debug || true",
);
e.arg("pool", "console");

e.config_var_or("converter-flags", "cider.converter-flags", "");
e.config_var_or("cider-flags", "cider.flags", "");

e.rule(
"run-cider",
"$cider-exe -l $calyx-base --data data.dump $cider-flags $in > $out",
"$cider-exe -l $calyx-base $data $cider-flags $in > $out",
);

e.rule("dump-to-interp", "$cider-converter --to cider $converter-flags $in > $out");
e.rule("interp-to-dump", "$cider-converter --to json $converter-flags $in > $out");
e.build_cmd(
["data.dump"],
"dump-to-interp",
["$sim_data"],
["$cider-converter"],
);

if has_data {
e.rule("dump-to-interp", "$cider-converter --to cider $converter-flags $in > $out");
e.build_cmd(
["data.dump"],
"dump-to-interp",
["$sim_data"],
["$cider-converter"],
);
}
}

op(
"calyx-to-cider",
[sim::sim_setup, c::calyx_setup],
[c::calyx_setup],
c::calyx_state,
cider_state,
|e, input, output| {
Expand All @@ -58,37 +75,38 @@ op(

op(
"cider",
[sim::sim_setup, c::calyx_setup, cider_setup],
[c::calyx_setup, cider_setup],
cider_state,
sim::dat,
|e, input, output| {
let out_file = "interp_out.dump";
let dependencies = if e.config_or("sim.data", "").is_empty() { [] } else { ["data.dump"] };
e.build_cmd(
[out_file],
"run-cider",
[input],
["data.dump"],
dependencies,
);
e.build_cmd(
[output],
"interp-to-dump",
[out_file],
["$sim_data", "$cider-converter"],
["$cider-converter"],
);
},
);

op(
"debug",
[
sim::sim_setup,
tb::standalone_setup,
c::calyx_setup,
cider_setup,
],
cider_state,
dbg,
|e, input, output| {
e.build_cmd([output], "run-cider-debug", [input], ["data.dump"]);
let dependencies = if e.config_or("sim.data", "").is_empty() { [] } else { ["data.dump"] };
e.build_cmd([output], "run-cider-debug", [input], dependencies);
},
);
29 changes: 9 additions & 20 deletions fud2/tests/snapshots/tests__test@calyx_through_cider_to_dat.snap
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,6 @@ build-tool = fud2
rule get-rsrc
command = $build-tool get-rsrc $out

python = python3
build json-dat.py: get-rsrc
rule hex-data
command = $python json-dat.py --from-json $in $out
rule json-data
command = $python json-dat.py --to-json $out $in
sim_data = /test/data.json
datadir = sim_data
build $datadir: hex-data $sim_data | json-dat.py
rule sim-run
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

calyx-base = /test/calyx
calyx-exe = $calyx-base/target/debug/calyx
args =
Expand All @@ -32,21 +19,23 @@ rule calyx-with-flags

cider-exe = $calyx-base/target/debug/cider
cider-converter = $calyx-base/target/debug/cider-data-converter
rule run-cider-debug
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in debug || true
pool = console
converter-flags =
cider-flags =
data = --data data.dump
sim_data = /test/data.json
rule run-cider-debug
command = $cider-exe -l $calyx-base $data $cider-flags $in debug || true
pool = console
rule run-cider
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
command = $cider-exe -l $calyx-base $data $cider-flags $in > $out
rule interp-to-dump
command = $cider-converter --to json $converter-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
build data.dump: dump-to-interp $sim_data | $cider-converter

build pseudo_cider: calyx-with-flags _from_stdin_calyx.futil
build interp_out.dump: run-cider pseudo_cider | data.dump
build _to_stdout_dat.json: interp-to-dump interp_out.dump | $sim_data $cider-converter
build _to_stdout_dat.json: interp-to-dump interp_out.dump | $cider-converter

default _to_stdout_dat.json
27 changes: 8 additions & 19 deletions fud2/tests/snapshots/tests__test@calyx_to_cider-debug.snap
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,6 @@ build-tool = fud2
rule get-rsrc
command = $build-tool get-rsrc $out

python = python3
build json-dat.py: get-rsrc
rule hex-data
command = $python json-dat.py --from-json $in $out
rule json-data
command = $python json-dat.py --to-json $out $in
sim_data = /test/data.json
datadir = sim_data
build $datadir: hex-data $sim_data | json-dat.py
rule sim-run
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

calyx-base = /test/calyx
calyx-exe = $calyx-base/target/debug/calyx
args =
Expand All @@ -34,17 +21,19 @@ build tb.sv: get-rsrc

cider-exe = $calyx-base/target/debug/cider
cider-converter = $calyx-base/target/debug/cider-data-converter
rule run-cider-debug
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in debug || true
pool = console
converter-flags =
cider-flags =
data = --data data.dump
sim_data = /test/data.json
rule run-cider-debug
command = $cider-exe -l $calyx-base $data $cider-flags $in debug || true
pool = console
rule run-cider
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
command = $cider-exe -l $calyx-base $data $cider-flags $in > $out
rule interp-to-dump
command = $cider-converter --to json $converter-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
build data.dump: dump-to-interp $sim_data | $cider-converter

build pseudo_cider: calyx-with-flags _from_stdin_calyx.futil
Expand Down
13 changes: 0 additions & 13 deletions fud2/tests/snapshots/tests__test@plan_calyx-to-cider.snap
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,6 @@ build-tool = fud2
rule get-rsrc
command = $build-tool get-rsrc $out

python = python3
build json-dat.py: get-rsrc
rule hex-data
command = $python json-dat.py --from-json $in $out
rule json-data
command = $python json-dat.py --to-json $out $in
sim_data = /test/data.json
datadir = sim_data
build $datadir: hex-data $sim_data | json-dat.py
rule sim-run
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

calyx-base = /test/calyx
calyx-exe = $calyx-base/target/debug/calyx
args =
Expand Down
29 changes: 9 additions & 20 deletions fud2/tests/snapshots/tests__test@plan_cider.snap
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,6 @@ build-tool = fud2
rule get-rsrc
command = $build-tool get-rsrc $out

python = python3
build json-dat.py: get-rsrc
rule hex-data
command = $python json-dat.py --from-json $in $out
rule json-data
command = $python json-dat.py --to-json $out $in
sim_data = /test/data.json
datadir = sim_data
build $datadir: hex-data $sim_data | json-dat.py
rule sim-run
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

calyx-base = /test/calyx
calyx-exe = $calyx-base/target/debug/calyx
args =
Expand All @@ -32,20 +19,22 @@ rule calyx-with-flags

cider-exe = $calyx-base/target/debug/cider
cider-converter = $calyx-base/target/debug/cider-data-converter
rule run-cider-debug
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in debug || true
pool = console
converter-flags =
cider-flags =
data = --data data.dump
sim_data = /test/data.json
rule run-cider-debug
command = $cider-exe -l $calyx-base $data $cider-flags $in debug || true
pool = console
rule run-cider
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
command = $cider-exe -l $calyx-base $data $cider-flags $in > $out
rule interp-to-dump
command = $cider-converter --to json $converter-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
build data.dump: dump-to-interp $sim_data | $cider-converter

build interp_out.dump: run-cider /input.ext | data.dump
build /output.ext: interp-to-dump interp_out.dump | $sim_data $cider-converter
build /output.ext: interp-to-dump interp_out.dump | $cider-converter

default /output.ext
27 changes: 8 additions & 19 deletions fud2/tests/snapshots/tests__test@plan_debug.snap
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,6 @@ build-tool = fud2
rule get-rsrc
command = $build-tool get-rsrc $out

python = python3
build json-dat.py: get-rsrc
rule hex-data
command = $python json-dat.py --from-json $in $out
rule json-data
command = $python json-dat.py --to-json $out $in
sim_data = /test/data.json
datadir = sim_data
build $datadir: hex-data $sim_data | json-dat.py
rule sim-run
command = ./$bin +DATA=$datadir +CYCLE_LIMIT=$cycle-limit $args > $out
cycle-limit = 500000000

build tb.sv: get-rsrc

calyx-base = /test/calyx
Expand All @@ -34,17 +21,19 @@ rule calyx-with-flags

cider-exe = $calyx-base/target/debug/cider
cider-converter = $calyx-base/target/debug/cider-data-converter
rule run-cider-debug
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in debug || true
pool = console
converter-flags =
cider-flags =
data = --data data.dump
sim_data = /test/data.json
rule run-cider-debug
command = $cider-exe -l $calyx-base $data $cider-flags $in debug || true
pool = console
rule run-cider
command = $cider-exe -l $calyx-base --data data.dump $cider-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
command = $cider-exe -l $calyx-base $data $cider-flags $in > $out
rule interp-to-dump
command = $cider-converter --to json $converter-flags $in > $out
rule dump-to-interp
command = $cider-converter --to cider $converter-flags $in > $out
build data.dump: dump-to-interp $sim_data | $cider-converter

build /output.ext: run-cider-debug /input.ext | data.dump
Expand Down
8 changes: 4 additions & 4 deletions interp/tests/complex/unsigned-dot-product.futil
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ component main() -> () {
@external mult = std_mult_pipe(32);
}
wires {
comb group is_less_than<"static"=0> {
comb group is_less_than {
lt0.left = counter.out;
lt0.right = 3'd4;
} // Control segment for `counter` < `4`.
Expand Down Expand Up @@ -70,13 +70,13 @@ component main() -> () {
initialize_mem_3[done] = mem0.done & mem1.done ? 1'd1;
}

group initialize_counter<"static"=1> {
group initialize_counter {
counter.in = 3'd0;
counter.write_en = 1'd1;
initialize_counter[done] = counter.done;
}

group incr_counter<"static"=1> {
group incr_counter {
counter.write_en = 1'd1;
add0.left = counter.out;
add0.right = 3'd1; // Increment by 1.
Expand All @@ -100,7 +100,7 @@ component main() -> () {
mul[done] = t.done;
}

group add<"static"=1> {
group add {
add1.left = t.out;
add1.right = r_2.out;
r_2.write_en = 1'd1;
Expand Down
2 changes: 1 addition & 1 deletion interp/tests/control/while.futil
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ component main() -> () {
cond[done] = lt_reg.done;
}

group incr<"static"=1> {
group incr {
i.write_en = 1'b1;
i.write_data = add.out;
i.addr0 = 1'd0;
Expand Down
4 changes: 2 additions & 2 deletions interp/tests/primitives/mem.futil
Original file line number Diff line number Diff line change
Expand Up @@ -8,14 +8,14 @@ component main() -> () {
}

wires {
group write<"static"=1> {
group write {
mem.write_en = 1'd1;
mem.addr0 = 1'd0;
mem.write_data = 32'd9;
write[done] = mem.done;
}

group read<"static"=1> {
group read{
mem.addr0 = 1'd0;
reg0.write_en = 1'd1;
reg0.in = mem.read_data;
Expand Down
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