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more tests and small tweaks
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ayakayorihiro committed Nov 12, 2024
1 parent 3639e21 commit 0126ede
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Showing 4 changed files with 80 additions and 4 deletions.
8 changes: 4 additions & 4 deletions calyx-opt/src/passes/profiler_instrumentation.rs
Original file line number Diff line number Diff line change
Expand Up @@ -63,11 +63,11 @@ impl Visitor for ProfilerInstrumentation {
let invoked_group_name =
parent_group_ref.upgrade().borrow().name();
let guard = *(assigment_ref.guard.clone());
let combined_guard: Guard<Nothing> = Guard::And(
Box::new(guard),
Box::new(Guard::Not(Box::new(Guard::port(
let combined_guard: Guard<Nothing> = Guard::and(
guard,
Guard::Not(Box::new(Guard::port(
done_port_ref.clone(),
)))),
))),
);
match self.group_map.get_mut(&invoked_group_name) {
Some(vec_ref) => {
Expand Down
32 changes: 32 additions & 0 deletions tests/passes/inline-structural-group-enables/cond.futil
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main() -> () {
cells {
@external(1) a = comb_mem_d1(32, 1, 1);
lt = std_lt(32);
}

wires {
comb group cond {
lt.left = 32'd5;
lt.right = 32'd9;
}

group wr_a {
a.addr0 = 1'b0;
a.write_en = 1'b1;
a.write_data = 32'd1;
wr_a[done] = a.done;
}

group wr_b {
wr_a[go] = lt.out ? 1'b1;
wr_b[done] = wr_a[done];
}
}

control {
wr_b;
}
}
12 changes: 12 additions & 0 deletions tests/passes/inline-structural-group-enables/cond.futil.data
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
{
"a": {
"data": [
0
],
"format": {
"numeric_type": "bitnum",
"is_signed": true,
"width": 32
}
}
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
{
"a": {
"data": [
0
],
"format": {
"numeric_type": "bitnum",
"is_signed": true,
"width": 32
}
},
"b": {
"data": [
0
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
},
"c": {
"data": [
0
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
}
}

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