made import statement in _toVHDL.py more specific and fixed warning i…

…n _VHDLNameValidation
bmindur · Sep 2, 2016 · 0d6a5d7 · 0d6a5d7
1 parent 7f31b57
commit 0d6a5d7
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Showing 2 changed files with 10 additions and 9 deletions.
diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py
@@ -1,5 +1,6 @@
 import warnings
 from myhdl import *
+from myhdl import ToVHDLWarning
 from myhdl.conversion import _analyze
 import pytest
 
@@ -34,13 +35,13 @@
 def _nameValid(name):
     for keyword in _vhdl_keywords:
         if name == keyword:
-            warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning)
+            warnings.warn("VHDL keyword used: %s" % (name), category=ToVHDLWarning)
     for saved_name in _usedNames:
         if name.lower() == saved_name:
-            warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning)
-    _usedNames.append(name).lower
+            warnings.warn("Previously used name being reused: %s" % (name), category=ToVHDLWarning)
+    _usedNames.append(name.lower())
     if name[0] == '_':
-        warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning)
+        warnings.warn("VHDL variable names cannot contain '_': %s" % (name), category=ToVHDLWarning)
     for char in name:
         if char == '-':
-            warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning)
+            warnings.warn("VHDL variable names cannot contain '-': %s" % (name), category=ToVHDLWarning)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
@@ -55,7 +55,7 @@
 from myhdl._util import _flatten
 from myhdl._compat import integer_types, class_types, StringIO
 from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
-import myhdl.conversion._VHDLNameValidation 
+from myhdl.conversion._VHDLNameValidation import _nameValid
 
 
 from myhdl._block import _Block
@@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor
             if convertPort:
                 pt = "std_logic_vector"
              # Check if VHDL keyword or reused name
-            _VHDLNameValidation._nameValid(s)
+            _nameValid(s)
             if s._driven:
                 if s._read:
                     if not isinstance(s, _TristateSignal):
@@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
             print("signal %s: %s%s;" % (s._name, p, r), file=f)
         elif s._read:
             # Check if VHDL keyword or reused name
-            _VHDLNameValidation._nameValid(s)
+            _nameValid(s)
             # the original exception
             # raise ToVHDLError(_error.UndrivenSignal, s._name)
             # changed to a warning and a continuous assignment to a wire
@@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
         if not m._driven and not m._read:
             continue
         # Check if VHDL keyword or reused name
-        _VHDLNameValidation._nameValid(m)
+        _nameValid(m)
         r = _getRangeString(m.elObj)
         p = _getTypeString(m.elObj)
         t = "t_array_%s" % m.name