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CC1120 Driver
The CC1120 is a high performance, low power RF transceiver designed to operate with a companion MCU - the Arduino Due - in BLUEsat's CubeSat for the Canadian Satellite Design Challenge. The OBC will interface with the CC1120 over a 4-wire SPI interface, allowing the CC1120 to be configured and programmed into different modes (see command strobe), read and write buffered data, and read status information. The CC1120 will automate all common RF related tasks, greatly offloading the OBC on the Arduino Due.
The following key parameters can be programmed using the SPI interface.
- Power-down/power-up mode (SLEEP/IDLE)
- Crystal oscillator power-up/power-down (IDLE/XOFF)
- Receive/transmit mode (RX/TX)
- Carrier frequency
- Symbol rate
- Modulation format
- RX channel filter bandwidth
- RF output power
- Data buffering with separate 128-byte receive and transmit FIFOs
- Packet radio hardware support
- Data whitening
- Enhanced Wake-On-Radio (eWOR)
The CC1120 Driver is located in src > Drivers > CC1120
The CC1120 can be configured using TI's SmartRF Studio software. The software is very useful for evaluating performance and debugging. The software is used alongside the TreEB with a the MSP430 USB-Debug-Interface. BLUEsat has two TrxEB's available and one MSP430.
Saleae Logic and the Logic Analyser can be used to sniff the SPI lines to monitor communication and debug. There is only one Logic Analyser available in BLUEsat.
CC1120 is configured through a 4-wire SPI interface where CC1120 is the slave.
- All transfers are done with the most significant bit first.
- All transactions start with a header byte containing:
- Read/Write bit (R/W). 0 is write and 1 is read.
- a Burst Bit (B). The Burst Bit allows registers with consecutive addresses to be accessed efficiently. An internal address counter will start at the 6-bit address provided in the header an increment by one each new byte. Burst access is terminated by setting CSn high.
- a 6-Bit Address. Refer to the [SPI Address Space](SPI Address Space) for its different uses.
- A status byte is sent on the SO pin each time a header byte is transmitted in the SI pin.
- The CSn pin must be kept low during transfers over SPI.
- When the CSn is pulled low, the SO pin must go low before starting to transfer the header byte.
- The SO pin will always go low immediately, unless the chip was in SLEEP or XOFF state, or it has been misconfigured.
Fill in later, it's on page 8, Table 1 of the User's Guide linked at the bottom.
Table 1. SPI Address Space
| Name | Address |
|---|---|
| Register Space | 0x00 |
| ... | ... |
| Register Space | 0x2E |
| Extended Register Space | 0x2F |
| Command Strobes | 0x30 |
| ... | ... |
| Command Strobes | 0x3D |
| Direct Memory Access | 0x3E |
| FIFO Access (push/pop) | 0x3F |
The configuration registers on the CC112X are located on SPI addresses from 0x00 to 0x2E, as shown in Table 1, with the address extension command at address 0x2F to access the Extended Register Space. The Extended Register Space and Direct Memory Access allow access to 256 more addresses each (0xFF = 16*16). All configuration registers can be written to and read from, and this is controlled by the R/W bit in the header byte. All configuration registers can also be accessed with the burst bit set to either 1 or 0.
Note that all registers in register space have retention. In extended register space, the status registers and FIFO pointers do not have retention.
Command Strobes can be viewed as single byte instructions to CC1120. The command strobe registers, with addresses shown in Table 1, are accessed by transferring a single header byte (no data is being transferred). The status byte is available on the SO pin when a command strobe is being sent.
- The Read/Write Bit can be set to either 0 or 1.
- The Burst Bit must be 0.
- The six address bits range from 0x30 to 0x3D. A command strobe can be followed by any other SPI access without pulling CSn high. The command strobes are executed immediately (except for SRES, SPWD, SWOR, and SXOFF). When a SRES strobe is issued, the CSN pin must be kept low and wait for SO to go low again before the next header byte can be issued.
| Address | Strobe Name | Description |
|---|---|---|
| 0x30 | SRES | Reset chip |
| 0x31 | SFSTXON | Enable and calibrate frequency synthesizer (if SETTLING_CFG.FS_AUTOCAL = 1). If in RX and PKT_CFG2.CCA_MODE != 0: Go to a wait state where only the synthesizer is running (for quick RX/TX turnaround). |
| 0x32 | SXOFF | Enter XOFF state when CSn is de-asserted |
| 0x33 | SCAL | Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (SETTLING_CFG.FS_AUTOCAL = 0) |
| 0x34 | SRX | Enable RX. Perform calibration first if coming from IDLE and SETTLING_CFG.FS_AUTOCAL = 1 |
| 0x35 | STX | In IDLE state: Enable TX. Perform calibration first if SETTLING_CFG.FS_AUTOCAL = 1. If in RX state and PKT_CFG2.CCA_MODE != 0: Only go to TX if channel is clear |
| 0x36 | SIDLE | Exit RX/TX, turn off frequency synthesizer and exit eWOR mode if applicable |
| 0x37 | SAFC | Automatic Frequency Compensation |
| 0x38 | SWOR | Start automatic RX polling sequence (eWOR) if WOR_CFG0.RC_PD = 0 |
| 0x39 | SPWD | Enter SLEEP mode when CSn is de-asserted |
| 0x3A | SFRX | Flush the RX FIFO. Only issue SFRX in IDLE or RX_FIFO_ERR states |
| 0x3B | SFTX | Flush the TX FIFO. Only issue SFTX in IDLE or TX_FIFO_ERR states |
| 0x3C | SWORRST | Reset the eWOR timer to the Event1 value |
| 0x3D | SNOP | No operation. May be used to get access to the chip status byte |
- FIFOs are mapped in Direct Memory Access (accessed by command 0x3E).
- TXFIFO: 0x00 - 0x7F
- RXFIFO: 0x80 - 0xFF
- The FIFO pointers are located in Extended Register Space (accessed by command 0x2F; addresses 0xD2 - 0xD5).
- 0xD2 - RXFIRST
- 0xD3 - RXLAST
- 0xD4 - TXFIRST
- 0xD5 - TXLAST
- Neither the TX or RX FIFOs have retention.
- Both FIFO data and pointers are readable and write-able.
TX FIFO is used by writing data into it, and then sending command strobe STX to transmit the packet to the air and move TXFIRST to the next packet. Details depend on how the radio is configured. Strobe STX will transmit from TXFIRST until the next packet begins or TXLAST is reached. You can transmit a single packet repeatedly by writing the address of the packet to TXFIRST, strobing STX, and repeating.
It's late and I'm tired.
The TX and RX FIFOs can also be accessed using the standard FIFO push/pop interface with the 0x3F address. When the R/W Bit is 0 the TX FIFO is accessed; when the R/W Bit is 1 the RX FIFO is accessed. Using this access the TX FIFO is write-only and the RX FIFO is read-only. Burst access is available.
The single byte access method expects a header byte and one data byte. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting the CSn high.
If the radio tries to write to the RX FIFO after it is full or if the RX FIFO is tried read when it is empty, the RXFIFO_OVERFLOW and RXFIFO_UNDERFLOW signals will be asserted and the radio will enter the RX_FIFO_ERR state. Likewise, if the TX FIFO is tried written when it is full or if the TX FIFO runs empty in the middle of a packet, the TXFIFO_OVERFLOW and TXFIFO_UNDERFLOW signals will be asserted and the radio will enter the TX_FIFO_ERR state.
A SFTX command strobe wiull flush the RX FIFO. A SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TX_FIFO_ERR, or RX_FIFO_ERR states. Both FIFOs are flushed when going to the SLEEP state.
We can configure the GPIO pins to do cool things like MCU input and interrupt, wake-ups, and send status signals.
See complete glossary here.
| Acronym | Phrase |
|---|---|
| CSn | Chip Select (same as SS) |
| eWOR | Enhanced Wake-On-Radio |
| FIFO | First In, First Out |
| MCU | Microcontroller |
| MISO | Master Input, Slave Output |
| MOSI | Master Output, Slave Input |
| OBC | On Board Computer |
| RX | Receive |
| RF | Radio Frequency |
| SCLK | Serial Clock |
| SI | Slave Input (same as MOSI) |
| SO | Slave Output (same as MISO) |
| SPI | Serial Peripheral Interface |
| SS | Slave Select |
| TX | Transmit |