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Export local counter from timeWb component. #729

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Mar 3, 2025
Merged

Export local counter from timeWb component. #729

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2 changes: 1 addition & 1 deletion bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs
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Expand Up @@ -97,7 +97,7 @@ vexRiscvInner jtagIn0 uartRx =
[timeBus, uartBus, statusRegisterBus] <- processingElement NoDumpVcd peConfig -< jtag
(uartTx, _uartStatus) <-
uartInterfaceWb @dom d16 d16 (uartDf baud) -< (uartBus, uartRx)
timeWb -< timeBus
_localCounter <- timeWb -< timeBus
testResult <- statusRegister -< statusRegisterBus
idC -< (testResult, uartTx)

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2 changes: 1 addition & 1 deletion bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs
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Expand Up @@ -100,7 +100,7 @@ vexRiscGmii SNat sysClk sysRst rxClk rxRst txClk txRst fwd =
( circuit $ \(uartTx, gmiiRx, jtag) -> do
[uartBus, timeBus, wbAxiRx, wbAxiTx, dnaWb, gpioWb, macWb] <- pe -< jtag
(uartRx, _uartStatus) <- uart -< (uartBus, uartTx)
time -< timeBus
_localCounter <- time -< timeBus
_dna <- dnaC -< dnaWb
macStatIf -< (macWb, macStatus)
gpioDf <- idleSource -< ()
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2 changes: 1 addition & 1 deletion bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs
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Expand Up @@ -50,7 +50,7 @@ vexRiscUartHello diffClk rst_in =
[uartBus, timeBus] <- processingElement @Basic200 NoDumpVcd peConfig -< jtag
(uartTx, _uartStatus) <-
uartInterfaceWb d16 d16 (uartDf $ SNat @921600) -< (uartBus, uartRx)
timeWb -< timeBus
_localCounter <- timeWb -< timeBus
idC -< uartTx
where
(clk200, rst200_) = clockWizardDifferential diffClk noReset
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2 changes: 1 addition & 1 deletion bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs
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Expand Up @@ -90,7 +90,7 @@ dut localCounter dnaA dnaB = circuit $ do
(uartRx, jtagIdle) <- idleSource -< ()
[uartBus, timeBus, peBusA, peBusB] <- processingElement NoDumpVcd peConfig -< jtagIdle
(uartTx, _uartStatus) <- uartInterfaceWb d16 d2 uartSim -< (uartBus, uartRx)
timeWb -< timeBus
_localCounter <- timeWb -< timeBus
linkAB <- switchDemoPeWb d2 localCounter -< (peBusA, dnaAC, linkBA)
linkBA <- switchDemoPeWb d2 localCounter -< (peBusB, dnaBC, linkAB)
dnaAC <- signalToCSignal dnaA -< ()
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2 changes: 1 addition & 1 deletion bittide-instances/tests/Wishbone/Time.hs
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Expand Up @@ -70,7 +70,7 @@ dut = withClockResetEnable clockGen resetGen enableGen
(uartRx, jtag) <- idleSource -< ()
[uartBus, timeBus] <- processingElement NoDumpVcd peConfig -< jtag
(uartTx, _uartStatus) <- uartInterfaceWb d2 d2 uartSim -< (uartBus, uartRx)
timeWb -< timeBus
_localCounter <- timeWb -< timeBus
idC -< uartTx
where
(iMem, dMem) =
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2 changes: 1 addition & 1 deletion bittide-instances/tests/Wishbone/Watchdog.hs
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Expand Up @@ -67,7 +67,7 @@ dut = withClockResetEnable clockGen resetGen enableGen
<| (watchDogWb @_ @_ @4 "50 us" (SNat @(PeriodToCycles Basic200 (Microseconds 50))))
-< idleBusB

timeWb <| (watchDogWb @_ @_ @4 "" d0) -< timeBus
_localCounter <- timeWb <| (watchDogWb @_ @_ @4 "" d0) -< timeBus
(uartTx, _uartStatus) <- (uartInterfaceWb @_ @_ @4) d2 d2 uartSim -< (uartBus, uartRx)
idC -< uartTx
where
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6 changes: 3 additions & 3 deletions bittide/src/Bittide/Wishbone.hs
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Expand Up @@ -578,11 +578,11 @@ timeWb ::
, KnownNat addrW
, 1 <= DomainPeriod dom
) =>
Circuit (Wishbone dom 'Standard addrW (Bytes 4)) ()
timeWb = Circuit $ \(wbM2S, _) -> (mealy goMealy (False, 0, 0) wbM2S, ())
Circuit (Wishbone dom 'Standard addrW (Bytes 4)) (CSignal dom (Unsigned 64))
timeWb = Circuit $ \(wbM2S, _) -> unbundle $ mealy goMealy (False, 0, 0) wbM2S
where
goMealy (reqCmp0, scratch0 :: Unsigned 64, count :: Unsigned 64) wbM2S =
((reqCmp1, scratch1, succ count), wbS2M1)
((reqCmp1, scratch1, succ count), (wbS2M1, count))
where
freq = natToNum @(DomainToHz dom) :: Unsigned 64
RegisterBank (splitAtI -> (freqMsbs, freqLsbs)) = getRegsBe @8 freq
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