Add compare-sections to gdb scripts

.github/docker/build-and-publish.sh

@@ -13,13 +13,18 @@ TODAY="$(date +%F)"
 
 cd "${HERE}"
 
+# Copy files for caching purposes
 cp "${ROOT}/default.nix" .
 cp "${ROOT}/shell.nix" .
 cp "${ROOT}/rust-toolchain.toml" .
 cp -ap "${ROOT}/nix" .
 
 docker build -t "${REPO}/${NAME}:$TODAY" -t "${REPO}/${NAME}:latest" .
 
+# Clean up copied files
+rm default.nix shell.nix rust-toolchain.toml
+rm -rf nix
+
 read -p "Push to GitHub? (y/N) " push
 
 if [[ $push =~ ^[Yy]$ ]]; then

.github/workflows/ci.yml

@@ -60,7 +60,7 @@ jobs:
         shell: git-nix-shell {0} --option connect-timeout 360
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -119,7 +119,7 @@ jobs:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_SHA" --keep "S3_PASSWORD"
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -165,7 +165,7 @@ jobs:
      ]
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -225,7 +225,7 @@ jobs:
     needs: [build]
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -256,7 +256,7 @@ jobs:
     needs: [build]
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -297,7 +297,7 @@ jobs:
       run:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_SHA" --keep "S3_PASSWORD"
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
     needs: [build]
 
@@ -322,7 +322,7 @@ jobs:
       run:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_SHA" --keep "S3_PASSWORD"
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
     needs: [build]
 
@@ -350,7 +350,7 @@ jobs:
       run:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_SHA" --keep "S3_PASSWORD"
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
     needs: [build]
 
@@ -383,7 +383,7 @@ jobs:
     needs: [build]
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -410,7 +410,7 @@ jobs:
     needs: [build]
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -436,7 +436,7 @@ jobs:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_OUTPUT"
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -469,7 +469,7 @@ jobs:
         shell: git-nix-shell {0} --option connect-timeout 360 --pure --keep "GITHUB_OUTPUT"
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       options: --memory=11g
 
     steps:
@@ -528,7 +528,7 @@ jobs:
       fail-fast: false
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       volumes:
         - /opt/tools:/opt/tools
       options: --init --mac-address="6c:5a:b0:6c:13:0b" --memory=11g
@@ -608,7 +608,7 @@ jobs:
       fail-fast: false
 
     container:
-      image: ghcr.io/clash-lang/nixos-bittide-hardware:2024-11-20
+      image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-01-09
       volumes:
         - /opt/tools:/opt/tools
         - /dev:/dev

bittide-instances/bittide-instances.cabal

@@ -14,7 +14,6 @@ copyright: Copyright © 2022-2024 Google LLC
 data-files:
   -- Cabal is very picky about wildcards in `data-files`:
   -- https://cabal.readthedocs.io/en/3.6/cabal-package.html#pkg-field-data-files
-  data/**/*.gdb
   data/**/*.sh
   data/**/*.xdc
   data/**/*.yml

bittide-instances/data/constraints/jtag/pmod0.xdc

@@ -6,6 +6,5 @@
 # Note that AH18 is a global clock capable pin
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {JTAG_TCK}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {JTAG_TDI}]
-set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE26} [get_ports {JTAG_RST}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {JTAG_TMS}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {JTAG_TDO}]

bittide-instances/data/constraints/jtag/pmod1.xdc

@@ -6,7 +6,6 @@
 # Note that there are no clock capable pins in this list
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP16} [get_ports {JTAG_TCK}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP15} [get_ports {JTAG_TDI}]
-set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM16} [get_ports {JTAG_RST}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM15} [get_ports {JTAG_TMS}]
 set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN18} [get_ports {JTAG_TDO}]
 

bittide-instances/data/openocd/start.sh

@@ -17,6 +17,6 @@ mkdir -p "${stderr_dir}"
 OPENOCD_STDERR_LOG="$(realpath ${OPENOCD_STDERR_LOG})"
 
 cd $(dirname $0)
-exec openocd-vexriscv -f ports.tcl -f sipeed.tcl -f vexriscv_init.tcl $@ \
+exec openocd-riscv -f ports.tcl -f sipeed.tcl -f vexriscv_init.tcl $@ \
   > >(tee "${OPENOCD_STDOUT_LOG}") \
   2> >(tee "${OPENOCD_STDERR_LOG}" >&2)

bittide-instances/data/openocd/vexriscv_init.tcl

@@ -8,36 +8,20 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
   # set useful default
-   set _CPUTAPID 0x10001fff
+   set _CPUTAPID 0x10002FFF
 }
 
-set _CHIPNAME vexrisc_ocd
+set _CHIPNAME riscv
 
 # The JTAG TAP itself is given the name "bridge", because it refers to the
 # JtagBridge that's part of the VexRiscv/SpinalHDL debug infrastructure.
 # In the example design, there is the JtagBridge controls a single CPU, but
 # the capability is there for 1 JTAG TAP + JtagBridge to control multiple
 # VexRiscv CPUs.
-jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF
+jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 5
 
 # There is 1 CPU controlled by the "bridge" JTAG TAP, "cpu0"
-target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge
-
-# The JtagBridge/SystemDebugger receives commands in a serialized way. It gets synchronized into
-# a parallel bus, and a response is received. Along the way, there may be various clock domain
-# crossings or pipeline delays.
-# readWaitCycles instructs OpenOCD to insert idle JTAG clock cycles before shifting out
-# the response.
-# There aren't many transactions where read-back throughput is important, so there's little
-# points in lowballing this number.
-vexriscv readWaitCycles 10
-
-# When the Verilog of a SpinalHDL design with one or more VexRiscv CPUs is created, the system
-# also creates a .yaml file with information that's sideband information that's important for
-# OpenOCD to control the CPU correctly.
-# A good example of this are the number of hardware breakpoints that are supported by the CPU.
-set git_top_level [string trim [exec git rev-parse --show-toplevel]]
-vexriscv cpuConfigFile [file join $git_top_level clash-vexriscv clash-vexriscv example-cpu ExampleCpu.yaml]
+target create $_CHIPNAME.cpu0 riscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge
 
 # The rate at which OpenOCD polls active JTAG TAPs to check if there has been a notable
 # event. (E.g. to check if the CPU has hit a breakpoint.)

bittide-instances/src/Bittide/Instances/Hitl/Driver/DnaOverSerial.hs

@@ -39,7 +39,7 @@ dnaOverSerialDriver ::
   String ->
   [(HwTarget, DeviceInfo)] ->
   VivadoM ExitCode
-dnaOverSerialDriver _name targets = do
+dnaOverSerialDriver testName targets = do
   results <- brackets (liftIO <$> initPicocoms) (liftIO . snd) $ \initPicocomsData -> do
     let targetPicocoms = fst <$> initPicocomsData
 
@@ -72,7 +72,7 @@ dnaOverSerialDriver _name targets = do
 
     projectDir <- findParentContaining "cabal.project"
     let
-      hitlDir = projectDir </> "_build" </> "hitl"
+      hitlDir = projectDir </> "_build" </> "hitl" </> testName
       stdoutLog = hitlDir </> "picocom-stdout." <> show targetIndex <> ".log"
       stderrLog = hitlDir </> "picocom-stderr." <> show targetIndex <> ".log"
     putStrLn $ "logging stdout to `" <> stdoutLog <> "`"