MAGIC: 4

bittide · Mar 4, 2025 · 925f743 · 925f743
1 parent f77b338
commit 925f743
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Ugns.hs b/bittide-instances/src/Bittide/Instances/Ugns.hs
@@ -94,7 +94,7 @@ toCounterMap fpgaIndexed = goSrc <$> indicesI
   goSrcDst src dst | src == dst = Nothing
   goSrcDst src dst =
     let (srcCycle, dstCycle) = fpgaIndexed !! dst Map.! src
-     in Just (dst, srcCycle - dstCycle)
+     in Just (dst, srcCycle - dstCycle + 4) -- MAGIC: seems to fix internal latency???
 
 uncons :: (HasCallStack) => Vec (n + 1) a -> (a, Vec n a)
 uncons (x :> xs) = (x, xs)

diff --git a/bittide/src/Bittide/SwitchDemoProcessingElement.hs b/bittide/src/Bittide/SwitchDemoProcessingElement.hs
@@ -67,19 +67,20 @@ switchDemoPe SNat localCounter linkIn dna readStart readCycles writeStart writeC
     dnaVec :: Signal dom (Vec 2 (BitVector 64))
     dnaVec = reverse . bitCoerce . zeroExtend <$> dna
 
-  linkOut = stateToLinkOutput <$> peState <*> buffer <*> localData
+  linkOut = stateToLinkOutput <$> peState <*> buffer <*> localData <*> dna
 
   stateToLinkOutput ::
     SimplePeState bufferSize ->
     Vec (bufferSize * 3) (BitVector 64) ->
     Vec 3 (BitVector 64) ->
+    BitVector 96 ->
     BitVector 64 -- also output boolean?
-  stateToLinkOutput state buf locData =
+  stateToLinkOutput state buf locData dna0 =
     case state of
       Write i
         | i <= 2 -> locData !! i
         | otherwise -> buf !! (i - 3)
-      _ -> 0xAAAA_BBBB_AAAA_BBBB
+      _ -> resize $ complement dna0
 
   -- \| The buffer stores all the incoming bittide data. For the Bittide Switch demo,
   -- each FPGA sends its DNA and local clock cycle counter, along with all received data.