fixup! (DROPME) Fix up debugging ILA

bittide · Feb 21, 2025 · 67f3889 · 67f3889
1 parent 496175d
commit 67f3889
Showing 1 changed file with 26 additions and 2 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs b/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs
@@ -59,6 +59,7 @@ import Clash.Cores.Xilinx.VIO (vioProbe)
 import Clash.Cores.Xilinx.Xpm.Cdc (xpmCdcArraySingle, xpmCdcSingle)
 import Clash.Functor.Extra ((<<$>>))
 import Clash.Sized.Extra (unsignedToSigned)
+import Clash.Sized.Vector.ToTuple (vecToTuple)
 import Clash.Xilinx.ClockGen (clockWizardDifferential)
 import Protocols
 import Protocols.Wishbone
@@ -210,6 +211,13 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
           :> "dd_nFincs"
           :> "dd_nFdecs"
           :> "dd_netFincs"
+          :> "dd_dDiff0"
+          :> "dd_dDiff1"
+          :> "dd_dDiff2"
+          :> "dd_dDiff3"
+          :> "dd_dDiff4"
+          :> "dd_dDiff5"
+          :> "dd_dDiff6"
           :> Nil
       )
         { depth = D32768
@@ -227,6 +235,13 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
       nFincs
       nFdecs
       (fmap unsignedToSigned nFincs - fmap unsignedToSigned nFdecs)
+      dDiff0
+      dDiff1
+      dDiff2
+      dDiff3
+      dDiff4
+      dDiff5
+      dDiff6
 
   captureFlag =
     riseEvery
@@ -267,6 +282,15 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
       )
       (satSucc SatBound <$> nFdecs)
 
+  ( dDiff0
+    , dDiff1
+    , dDiff2
+    , dDiff3
+    , dDiff4
+    , dDiff5
+    , dDiff6
+    ) = vecToTuple domainDiffs
+
   -- Step 1, wait for SPI:
   (_, _, spiState, spiOut) =
     withClockResetEnable refClk spiRst enableGen
@@ -512,7 +536,7 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
     delay refClk enableGen minBound
       $ speedChangeToStickyPins
         refClk
-        handshakeRstFree
+        (unsafeFromActiveLow allProgrammed)
         enableGen
         (SNat @Si539xHoldTime)
         callistoResult.maybeSpeedChangeC
@@ -521,7 +545,7 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
   domainDiffs =
     zipWith3
       (domainDiffCounterExt refClk)
-      (repeat handshakeRstFree)
+      (repeat $ unsafeFromActiveLow allProgrammed)
       transceivers.rxClocks
       (repeat transceivers.txClock)