Add user words to transceiver input/output (simulation only)

Allows for accessing data at top entity boundaries. Prepares for a
multi-node simulation including transceivers.

bittide-instances/src/Bittide/Instances/Hitl/LinkConfiguration.hs

@@ -37,14 +37,14 @@ import Bittide.Hitl
 import Bittide.Instances.Hitl.Setup
 
 import Clash.Annotations.TH (makeTopEntity)
-import Clash.Cores.Xilinx.GTH
 import Clash.Cores.Xilinx.Xpm.Cdc.Handshake.Extra
 import Clash.Cores.Xilinx.Xpm.Cdc.Single
 import Clash.Xilinx.ClockGen
 import Data.Maybe (fromMaybe, isJust)
 
 import qualified Bittide.Transceiver as Transceiver
 import qualified Bittide.Transceiver.ResetManager as ResetManager
+import qualified Clash.Cores.Xilinx.GTH as Gth
 
 {- | Checks whether the received index matches with the corresponding
 entry in 'Bittide.Instances.Hitl.Setup.fpgaSetup' and sychronizes
@@ -115,11 +115,11 @@ transceiversStartAndObserve ::
   "SYSCLK" ::: Clock Basic125 ->
   "RST_LOCAL" ::: Reset Basic125 ->
   "MY_INDEX" ::: Signal Basic125 (Index FpgaCount) ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , "allReady" ::: Signal Basic125 Bool
   , "success" ::: Signal Basic125 Bool
   , "stats" ::: Vec LinkCount (Signal Basic125 ResetManager.Statistics)
@@ -209,11 +209,11 @@ linkConfigurationTest ::
   "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
   "SYSCLK_125" ::: DiffClock Ext125 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , "SYNC_OUT" ::: Signal Basic125 Bool
   , "spiDone" ::: Signal Basic125 Bool
   , ""
@@ -225,7 +225,7 @@ linkConfigurationTest ::
 linkConfigurationTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+  refClk = Gth.ibufds_gte3 refClkDiff :: Clock Ext200
   (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
 
   -- the test starts with a valid configuration coming in

bittide-instances/src/Bittide/Instances/Hitl/Setup.hs

@@ -9,7 +9,6 @@ module Bittide.Instances.Hitl.Setup (
   FpgaCount,
   LinkCount,
   FpgaId,
-  TransceiverWires,
 
   -- * Topology
   allHwTargets,
@@ -36,12 +35,6 @@ type FpgaCount = 8 :: Nat
 
 type LinkCount = FpgaCount - 1
 
-{- | Data wires from/to transceivers. No logic should be inserted on these
-wires. Should be considered asynchronous to one another - even though their
-domain encodes them as related.
--}
-type TransceiverWires dom n = Signal dom (BitVector n)
-
 channelNames :: Vec LinkCount String
 channelNames =
   "X0Y10" :> "X0Y9" :> "X0Y16" :> "X0Y17" :> "X0Y18" :> "X0Y19" :> "X0Y11" :> Nil

bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs

@@ -72,7 +72,6 @@ import Bittide.Instances.Hitl.Setup
 
 import Clash.Annotations.TH (makeTopEntity)
 import Clash.Class.Counter
-import Clash.Cores.Xilinx.GTH
 import Clash.Cores.Xilinx.Ila (Depth (..), IlaConfig (..), ila, ilaConfig)
 import Clash.Cores.Xilinx.VIO
 import Clash.Cores.Xilinx.Xpm (xpmCdcArraySingle)
@@ -87,6 +86,7 @@ import qualified Bittide.ClockControl.StabilityChecker as SI
 import qualified Bittide.Instances.Hitl.Driver.SwCcTopologies as D
 import qualified Bittide.Transceiver as Transceiver
 import qualified Bittide.Transceiver.ResetManager as ResetManager
+import qualified Clash.Cores.Xilinx.GTH as Gth
 import qualified Data.Map.Strict as Map (fromList)
 
 {- $setup
@@ -228,15 +228,15 @@ topologyTest ::
   "SMA_MGT_REFCLK_C" ::: Clock Ext200 ->
   "SYSCLK" ::: Clock Basic125 ->
   "ILA_CTRL" ::: IlaControl Basic125 ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
   "TEST_CFG" ::: Signal Basic125 TestConfig ->
   "PROG_EN" ::: Reset Basic125 ->
   "CALIBRATED_SHIFT" ::: Signal Basic125 FincFdecCount ->
   "JTAG" ::: Signal Basic125 JtagIn ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , "FINC_FDEC" ::: Signal Basic125 (FINC, FDEC)
   , "CALLISTO_RESULT" ::: Signal Basic125 (CallistoResult LinkCount)
   , "CALLISTO_RESET" ::: Reset Basic125
@@ -756,12 +756,12 @@ swCcTopologyTest ::
   "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
   "SYSCLK_125" ::: DiffClock Ext125 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
   "JTAG" ::: Signal Basic125 JtagIn ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , ""
       ::: ( "FINC" ::: Signal Basic125 Bool
           , "FDEC" ::: Signal Basic125 Bool
@@ -778,7 +778,7 @@ swCcTopologyTest ::
 swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso jtagIn =
   hwSeqX tleDebugIla (txns, txps, unbundle swFincFdecs, syncOut, spiDone, spiOut, jtagOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+  refClk = Gth.ibufds_gte3 refClkDiff :: Clock Ext200
   (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
   ilaControl@IlaControl{..} = ilaPlotSetup IlaPlotSetup{..}
   startTest = isJust <$> testConfig
@@ -954,12 +954,12 @@ swCcOneTopologyTest ::
   "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
   "SYSCLK_125" ::: DiffClock Ext125 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
   "JTAG" ::: Signal Basic125 JtagIn ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , ""
       ::: ( "FINC" ::: Signal Basic125 Bool
           , "FDEC" ::: Signal Basic125 Bool

bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs

@@ -35,12 +35,12 @@ import Bittide.Instances.Hitl.Setup
 import Bittide.Transceiver
 
 import Clash.Annotations.TH (makeTopEntity)
-import Clash.Cores.Xilinx.GTH
 import Clash.Cores.Xilinx.Xpm.Cdc.Single (xpmCdcSingle)
 import Clash.Xilinx.ClockGen
 import Data.Maybe (fromMaybe, isJust)
 
 import qualified Bittide.Transceiver.ResetManager as ResetManager
+import qualified Clash.Cores.Xilinx.GTH as Gth
 import qualified Clash.Explicit.Prelude as E
 import qualified Data.List as L
 import qualified Data.Map as Map
@@ -84,11 +84,11 @@ goTransceiversUpTest ::
   "SMA_MGT_REFCLK_C" ::: Clock Ext200 ->
   "SYSCLK" ::: Clock Basic125 ->
   "RST_LOCAL" ::: Reset Basic125 ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , "allUp" ::: Signal Basic125 Bool
   , "anyErrors" ::: Signal Basic125 Bool
   , "stats" ::: Vec LinkCount (Signal Basic125 ResetManager.Statistics)
@@ -182,11 +182,11 @@ transceiversUpTest ::
   "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
   "SYSCLK_125" ::: DiffClock Ext125 ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
-  "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
-  "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
+  "GTH_RX_NS" ::: Gth.Wires GthRxS GthRx LinkCount ->
+  "GTH_RX_PS" ::: Gth.Wires GthRxS GthRx LinkCount ->
   "MISO" ::: Signal Basic125 Bit ->
-  ( "GTH_TX_NS" ::: TransceiverWires GthTxS LinkCount
-  , "GTH_TX_PS" ::: TransceiverWires GthTxS LinkCount
+  ( "GTH_TX_NS" ::: Gth.Wires GthTxS GthTx LinkCount
+  , "GTH_TX_PS" ::: Gth.Wires GthTxS GthTx LinkCount
   , "SYNC_OUT" ::: Signal Basic125 Bool
   , "spiDone" ::: Signal Basic125 Bool
   , ""
@@ -198,7 +198,7 @@ transceiversUpTest ::
 transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   (txns, txps, syncOut, spiDone, spiOut)
  where
-  refClk = ibufds_gte3 refClkDiff :: Clock Ext200
+  refClk = Gth.ibufds_gte3 refClkDiff :: Clock Ext200
 
   (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
 

bittide/src/Bittide/Transceiver.hs

@@ -178,9 +178,9 @@ data Outputs n tx rx txS free = Outputs
   -- ^ See 'Output.txReady'
   , txSamplings :: Vec n (Signal tx Bool)
   -- ^ See 'Output.txSampling'
-  , txPs :: Signal txS (BitVector n)
+  , txPs :: Gth.Wires txS tx n
   -- ^ See 'Output.txP'
-  , txNs :: Signal txS (BitVector n)
+  , txNs :: Gth.Wires txS tx n
   -- ^ See 'Output.txN'
   , rxClocks :: Vec n (Clock rx)
   -- ^ See 'Output.rxClock'
@@ -196,7 +196,7 @@ data Outputs n tx rx txS free = Outputs
   -- ^ See 'Output.stats'
   }
 
-data Output tx rx tx1 rx1 txS free serializedData = Output
+data Output tx rx tx1 rx1 txS free = Output
   { txOutClock :: Clock tx1
   -- ^ Must be routed through xilinxGthUserClockNetworkTx or equivalent to get usable clocks
   , txReset :: Reset tx
@@ -207,9 +207,9 @@ data Output tx rx tx1 rx1 txS free serializedData = Output
   -- 'Input.txStart' to be asserted before starting to send 'txData'.
   , txSampling :: Signal tx Bool
   -- ^ Data is sampled from 'Input.txData'
-  , txP :: Signal txS serializedData
+  , txP :: Gth.Wire txS tx
   -- ^ Transmit data (and implicitly a clock), positive
-  , txN :: Signal txS serializedData
+  , txN :: Gth.Wire txS tx
   -- ^ Transmit data (and implicitly a clock), negative
   , rxOutClock :: Clock rx1
   -- ^ Must be routed through xilinxGthUserClockNetworkRx or equivalent to get usable clocks
@@ -227,7 +227,7 @@ data Output tx rx tx1 rx1 txS free serializedData = Output
   -- ^ Statistics exported by 'ResetManager.resetManager'. Useful for debugging.
   }
 
-data Input tx rx tx1 rx1 ref free rxS serializedData = Input
+data Input tx rx tx1 rx1 ref free rxS = Input
   { clock :: Clock free
   -- ^ Any "always on" clock
   , reset :: Reset free
@@ -246,8 +246,8 @@ data Input tx rx tx1 rx1 ref free rxS serializedData = Input
   -- ^ Channel name, example \"X0Y18\"
   , clockPath :: String
   -- ^ Clock path, example \"clk0-2\"
-  , rxN :: Signal rxS serializedData
-  , rxP :: Signal rxS serializedData
+  , rxN :: Gth.Wire rxS rx
+  , rxP :: Gth.Wire rxS rx
   , txData :: Signal tx (BitVector 64)
   -- ^ Data to transmit to the neighbor. Is first sampled one cycle after both
   -- 'Input.txStart' and 'Output.txReady' are asserted. Is continuously sampled
@@ -274,9 +274,9 @@ data Inputs tx rx ref free rxS n = Inputs
   -- ^ See 'Input.channelName'
   , clockPaths :: Vec n String
   -- ^ See 'Input.clockPath'
-  , rxNs :: Signal rxS (BitVector n)
+  , rxNs :: Gth.Wires rxS rx n
   -- ^ See 'Input.rxN'
-  , rxPs :: Signal rxS (BitVector n)
+  , rxPs :: Gth.Wires rxS rx n
   -- ^ See 'Input.rxP'
   , txDatas :: Vec n (Signal tx (BitVector 64))
   -- ^ See 'Input.txData'
@@ -330,8 +330,8 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
     , rxResets = map (.rxReset) outputs
     , rxDatas = map (.rxData) outputs
     , -- transceiver
-      txPs = pack <$> bundle (map (.txP) outputs)
-    , txNs = pack <$> bundle (map (.txN) outputs)
+      txPs = Gth.packWires (map (.txP) outputs)
+    , txNs = Gth.packWires (map (.txN) outputs)
     , -- free
       linkUps = map (.linkUp) outputs
     , linkReadys = map (.linkReady) outputs
@@ -347,14 +347,14 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
   -- this zipWithN became unusably slow when using more then ~4 transceivers.
   -- Unfortunately this means debugIla is broken now, when using more then 1 transceiver.
   outputs =
-    (go txClockNw)
-      <$> (iterateI (+ 1) 0) -- Note that the target type is only 3 bits, so this will
+    go txClockNw
+      <$> iterateI (+ 1) 0 -- Note that the target type is only 3 bits, so this will
       -- wrap around after 8 transceivers. This is fine, as we
       -- only use this for debugging.
       <*> inputs.channelNames
       <*> inputs.clockPaths
-      <*> (unbundle (unpack <$> inputs.rxNs))
-      <*> (unbundle (unpack <$> inputs.rxPs))
+      <*> Gth.unpackWires inputs.rxNs
+      <*> Gth.unpackWires inputs.rxPs
       <*> inputs.txDatas
       <*> inputs.txStarts
       <*> inputs.rxReadys
@@ -416,12 +416,12 @@ transceiverPrbs ::
   , KnownDomain free
   ) =>
   Config free ->
-  Input tx rx tx1 rx1 ref free rxS (BitVector 1) ->
-  Output tx rx tx1 rx1 txS free (BitVector 1)
+  Input tx rx tx1 rx1 ref free rxS ->
+  Output tx rx tx1 rx1 txS free
 transceiverPrbs = transceiverPrbsWith Gth.gthCore
 
 transceiverPrbsWith ::
-  forall tx rx tx1 rx1 ref free txS rxS serializedData.
+  forall tx rx tx1 rx1 ref free txS rxS.
   ( HasSynchronousReset tx
   , HasDefinedInitialValues tx
   , HasSynchronousReset rx
@@ -435,10 +435,10 @@ transceiverPrbsWith ::
   , KnownDomain ref
   , KnownDomain free
   ) =>
-  Gth.GthCore tx1 tx rx1 rx ref free txS rxS serializedData ->
+  Gth.GthCore tx1 tx rx1 rx ref free txS rxS ->
   Config free ->
-  Input tx rx tx1 rx1 ref free rxS serializedData ->
-  Output tx rx tx1 rx1 txS free serializedData
+  Input tx rx tx1 rx1 ref free rxS ->
+  Output tx rx tx1 rx1 txS free
 transceiverPrbsWith gthCore opts args@Input{clock, reset} =
   when opts.debugIla debugIla `hwSeqX` result
  where
@@ -524,8 +524,8 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
       { txSampling = txUserData
       , rxData = mux rxUserData (Just <$> alignedRxData0) (pure Nothing)
       , txReady = withLockRxTx rxReadyNeighborSticky
-      , txN
-      , txP
+      , txN = txN
+      , txP = txP
       , txOutClock
       , txReset
       , rxOutClock
@@ -550,10 +550,10 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
     , reset_rx_done
     , _txpmaresetdone_out
     , _rxpmaresetdone_out
-    , (rxCtrl0 :: Signal rx (BitVector 16))
-    , (rxCtrl1 :: Signal rx (BitVector 16))
-    , (rxCtrl2 :: Signal rx (BitVector 8))
-    , (rxCtrl3 :: Signal rx (BitVector 8))
+    , rxCtrl0 :: Signal rx (BitVector 16)
+    , rxCtrl1 :: Signal rx (BitVector 16)
+    , rxCtrl2 :: Signal rx (BitVector 8)
+    , rxCtrl3 :: Signal rx (BitVector 8)
     ) =
       gthCore
         args.channelName