Keep clockControlReset asserted while delayCount <== startupDelay

bittide · Jan 28, 2025 · 332546e · 332546e
1 parent 488758b
commit 332546e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -335,7 +335,7 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg prog
   -- Clock control
   clockControlReset =
     startupDelayRst
-      `orReset` unsafeFromActiveLow ((==) <$> delayCount <*> (startupDelay <$> cfg))
+      `orReset` unsafeFromActiveLow ((<=) <$> delayCount <*> (startupDelay <$> cfg))
 
   clockMod = callistoResult.maybeSpeedChange
   allStable0 = callistoResult.allStable