Remove extra reset

bittide · Feb 19, 2025 · 01c6f8e · 01c6f8e
1 parent ccf9874
commit 01c6f8e
Showing 1 changed file with 25 additions and 25 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -34,8 +34,8 @@ module Bittide.Instances.Hitl.SwCcTopologies (
 ) where
 
 import Clash.Explicit.Prelude hiding (PeriodToCycles)
+import Clash.Prelude(withClockResetEnable)
 import qualified Clash.Explicit.Prelude as E
-import Clash.Prelude (HiddenClockResetEnable, exposeReset, hasReset, withClockResetEnable)
 import qualified Prelude as P
 
 import Data.Functor ((<&>))
@@ -257,7 +257,7 @@ topologyTest ::
   , "noFifoUnderflows" ::: Signal Basic125 Bool
   , "JTAG" ::: Signal Basic125 JtagOut
   )
-topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg progEn ccs jtagIn =
+topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg _progEn ccs jtagIn =
   hwSeqX
     fincFdecIla
     ( transceivers.txNs
@@ -361,36 +361,36 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg prog
       (CccStabilityCheckerFramesize Basic125)
   ccConfig = SwControlConfig jtagIn (reframingEnabled <$> cfg) SNat SNat
 
-  callistoSwClockControlInner ::
-    forall nLinks eBufBits dom margin framesize.
-    ( HiddenClockResetEnable dom
-    , KnownNat nLinks
-    , KnownNat eBufBits
-    , 1 <= nLinks
-    , 1 <= eBufBits
-    , nLinks + eBufBits <= 32
-    , 1 <= framesize
-    , 1 <= DomainPeriod dom
-    ) =>
-    Reset dom ->
-    SwControlConfig dom margin framesize ->
-    Signal dom (BitVector nLinks) ->
-    Vec nLinks (Signal dom (RelDataCount eBufBits)) ->
-    Signal dom (CallistoResult nLinks)
-  callistoSwClockControlInner extraRst a b c =
-    exposeReset (callistoSwClockControl a b c) newReset
-   where
-    oldReset = unsafeToActiveHigh hasReset
-    extraRst1 = unsafeToActiveHigh extraRst
-    newReset = unsafeFromActiveHigh $ oldReset .&&. extraRst1
+  -- callistoSwClockControlInner ::
+  --   forall nLinks eBufBits dom margin framesize.
+  --   ( HiddenClockResetEnable dom
+  --   , KnownNat nLinks
+  --   , KnownNat eBufBits
+  --   , 1 <= nLinks
+  --   , 1 <= eBufBits
+  --   , nLinks + eBufBits <= 32
+  --   , 1 <= framesize
+  --   , 1 <= DomainPeriod dom
+  --   ) =>
+  --   Reset dom ->
+  --   SwControlConfig dom margin framesize ->
+  --   Signal dom (BitVector nLinks) ->
+  --   Vec nLinks (Signal dom (RelDataCount eBufBits)) ->
+  --   Signal dom (CallistoResult nLinks)
+  -- callistoSwClockControlInner extraRst a b c = (callistoSwClockControl a b c) oldReset
+  --   exposeReset (callistoSwClockControl a b c) oldReset
+  --  where
+  --   oldReset = unsafeToActiveHigh hasReset
+  --   extraRst1 = unsafeToActiveHigh extraRst
+  --   newReset = unsafeFromActiveHigh $ oldReset .||. extraRst1
 
   callistoResult =
     callistoClockControlWithIla @LinkCount @CccBufferSize
       transceivers.txClock
       sysClk
       clockControlReset
       ccConfig
-      (callistoSwClockControlInner progEn)
+      callistoSwClockControl
       IlaControl{..}
       (mask <$> cfg)
       (resize <<$>> domainDiffs)