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Add PE config calculator #7181

Add PE config calculator

Add PE config calculator #7181

Triggered via push March 3, 2025 15:29
Status Success
Total duration 36m 3s
Artifacts 11

ci.yml

on: push
Build dependencies
2m 23s
Build dependencies
bittide-instances hardware-in-the-loop test matrix generation
17s
bittide-instances hardware-in-the-loop test matrix generation
bittide-instances synthesis matrix generation
23s
bittide-instances synthesis matrix generation
license-check
17s
license-check
Basic linting
1m 8s
Basic linting
bittide-experiments unittests
47s
bittide-experiments unittests
Bittide tests
6m 8s
Bittide tests
Rust Lints
29s
Rust Lints
Firmware Support Unit Tests
2m 7s
Firmware Support Unit Tests
Firmware Limit Checks
54s
Firmware Limit Checks
bittide-instances doctests
1m 11s
bittide-instances doctests
bittide-instances unittests
1m 41s
bittide-instances unittests
Matrix: synth
Matrix: HITL
Generate clock control report
1m 59s
Generate clock control report
All jobs finished
3s
All jobs finished
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Annotations

2 warnings
HITL (transceiversUpTest, test)
No files were found with the provided path: _build/vivado/*/ila-data _build/hitl/*. No artifacts will be uploaded.
HITL (linkConfigurationTest, test)
No files were found with the provided path: _build/vivado/*/ila-data _build/hitl/*. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
CC-HITLT Plot Sources
2.45 MB
Clock Control Reports
321 KB
_build-linkConfigurationTest
12.1 MB
_build-safeDffSynchronizer
2.59 KB
_build-swCcOneTopologyTest
278 MB
_build-swCcOneTopologyTest-debug
26.2 MB
_build-transceiversUpTest
12.6 MB
_build-vexRiscvTcpTest
44.3 MB
_build-vexRiscvTcpTest-debug
93.8 KB
_build-vexRiscvTest
40.2 MB
_build-vexRiscvTest-debug
203 KB